soc/amd/common: Move PCIe CLKREQ programming under fsp
CLKREQ programming as currently implemented is completely dependent on FSP DXIO descriptors, so move under common/fsp/pci and rename the Kconfig to reflect the move. TEST=build google/{guybrush, skyrim, myst} Change-Id: I87b53d092ddc367b134c25949f9da7670a6a1d88 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin L Roth <gaumless@gmail.com>
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@ -55,7 +55,6 @@ config SOC_AMD_CEZANNE
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select SOC_AMD_COMMON_BLOCK_PCI
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select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
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select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
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select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ
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select SOC_AMD_COMMON_BLOCK_PM
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select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
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select SOC_AMD_COMMON_BLOCK_PSP_GEN2
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@ -74,6 +73,7 @@ config SOC_AMD_CEZANNE
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select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB
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select SOC_AMD_COMMON_FSP_DMI_TABLES
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select SOC_AMD_COMMON_FSP_PCI
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select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ
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select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
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select SOC_AMD_COMMON_BLOCK_XHCI
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select SSE2
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@ -16,10 +16,3 @@ config SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
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depends on SOC_AMD_COMMON_BLOCK_PCI
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help
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Select this option to use AMD common PCIe GPP driver.
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config SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ
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bool
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depends on SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
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help
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This option includes code to disable PCIe clock request if the corresponding
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PCIe device is disabled.
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@ -5,7 +5,6 @@ ramstage-y += amd_pci_util.c
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ramstage-y += pci_routing_info.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_prt.c
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER) += pcie_gpp.c
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ) += pcie_clk_req.c
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endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI
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@ -3,3 +3,10 @@ config SOC_AMD_COMMON_FSP_PCI
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select SOC_AMD_COMMON_BLOCK_PCI
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help
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This option enabled FSP to provide common PCI functions.
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config SOC_AMD_COMMON_FSP_PCIE_CLK_REQ
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bool
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depends on SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
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help
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This option includes code to disable PCIe clock request if the corresponding
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PCIe device is disabled.
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@ -1,6 +1,5 @@
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## SPDX-License-Identifier: GPL-2.0-only
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ifeq ($(CONFIG_SOC_AMD_COMMON_FSP_PCI),y)
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ramstage-y += pci_routing_info.c
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ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_PCI) += pci_routing_info.c
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endif # CONFIG_SOC_AMD_COMMON_FSP_PCI
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ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_PCIE_CLK_REQ) += pcie_clk_req.c
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@ -61,7 +61,6 @@ config SOC_AMD_REMBRANDT_BASE
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select SOC_AMD_COMMON_BLOCK_PCI
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select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
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select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
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select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ
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select SOC_AMD_COMMON_BLOCK_PM
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select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
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select SOC_AMD_COMMON_BLOCK_PSP_GEN2
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@ -82,6 +81,7 @@ config SOC_AMD_REMBRANDT_BASE
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select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB
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select SOC_AMD_COMMON_FSP_DMI_TABLES
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select SOC_AMD_COMMON_FSP_PCI
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select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ
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select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
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select SSE2
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select UDK_2017_BINDING
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@ -60,7 +60,6 @@ config SOC_AMD_PHOENIX
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select SOC_AMD_COMMON_BLOCK_PCI
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select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
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select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
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select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ
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select SOC_AMD_COMMON_BLOCK_PM
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select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
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select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct
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@ -80,6 +79,7 @@ config SOC_AMD_PHOENIX
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select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB
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select SOC_AMD_COMMON_FSP_DMI_TABLES
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select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct
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select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ
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select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
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select SSE2
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select UDK_2017_BINDING
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