diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index b6fc43d287..c4662123d0 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -275,8 +275,6 @@ struct soc_intel_alderlake_config {
 	int s0ix_enable;
 	/* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */
 	uint8_t tcss_d3_hot_disable;
-	/* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */
-	uint8_t tcss_d3_cold_disable;
 	/* Enable DPTF support */
 	int dptf_enable;
 
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 704f910a69..7789cec747 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -648,7 +648,7 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
 
 	/* D3Hot and D3Cold for TCSS */
 	s_cfg->D3HotEnable = !config->tcss_d3_hot_disable;
-	s_cfg->D3ColdEnable = CONFIG(D3COLD_SUPPORT) && !config->tcss_d3_cold_disable;
+	s_cfg->D3ColdEnable = CONFIG(D3COLD_SUPPORT);
 
 	s_cfg->UsbTcPortEn = 0;
 	for (int i = 0; i < MAX_TYPE_C_PORTS; i++) {