GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/hatch: Fixes to initial hatch mainboard checkin 

Incorporating some feedback to initial hatch mainboard checking
(CL:30169) that came in after the CL merged.

Updated the chromeos.fmd with the following,
* SI_ALL = 3MB
* SI_BIOS = 16MB

BUG=b:20914069
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/hatch -x -a -v

Change-Id: I4e311c68873f10f71314e44d3a714639a06dbee8
Signed-off-by: Shelley Chen <shchen@google.com>
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30296
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shelley Chen 2018-12-18 13:11:25 -08:00 committed by Patrick Georgi
parent 74e0390e74
commit 6bb563f29c
6 changed files with 29 additions and 106 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/google/hatch/Kconfig
View File

@ -23,10 +23,14 @@ if BOARD_GOOGLE_BASEBOARD_HATCH
config CHROMEOS config CHROMEOS
bool bool
default y default y
select EC_GOOGLE_CHROMEEC_SWITCHES
select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_SWITCH_ON
select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_USB
select GBB_FLAG_FORCE_DEV_BOOT_LEGACY select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
select GBB_FLAG_FORCE_MANUAL_RECOVERY select GBB_FLAG_FORCE_MANUAL_RECOVERY
select HAS_RECOVERY_MRC_CACHE
select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
select VBOOT_LID_SWITCH
config DEVICETREE config DEVICETREE
string string
@ -68,10 +72,6 @@ config MAX_CPUS
int int
default 8 default 8
config OVERRIDE_DEVICETREE
string
default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_HATCH
config TPM_TIS_ACPI_INTERRUPT config TPM_TIS_ACPI_INTERRUPT
int int
default 53 # GPE0_DW1_21 (GPP_C21) default 53 # GPE0_DW1_21 (GPP_C21)

37
src/mainboard/google/hatch/chromeos.c
View File

@ -29,29 +29,15 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
{-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
{-1, ACTIVE_HIGH, 0, "EC in RW"}, {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW),
"EC in RW"},
}; };
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
} }
static int cros_get_gpio_value(int type) int get_write_protect_state(void)
{ {
const struct cros_gpio *cros_gpios; return gpio_get(GPIO_PCH_WP);
size_t i, num_gpios = 0;
cros_gpios = variant_cros_gpios(&num_gpios);
for (i = 0; i < num_gpios; i++) {
const struct cros_gpio *gpio = &cros_gpios[i];
if (gpio->type == type) {
int state = gpio_get(gpio->gpio_num);
if (gpio->polarity == CROS_GPIO_ACTIVE_LOW)
return !state;
else
return state;
}
}
return 0;
} }
void mainboard_chromeos_acpi_generate(void) void mainboard_chromeos_acpi_generate(void)
@ -63,18 +49,3 @@ void mainboard_chromeos_acpi_generate(void)
chromeos_acpi_gpio_generate(cros_gpios, num_gpios); chromeos_acpi_gpio_generate(cros_gpios, num_gpios);
} }
int get_write_protect_state(void)
{
return cros_get_gpio_value(CROS_GPIO_WP);
}
int get_recovery_mode_switch(void)
{
return cros_get_gpio_value(CROS_GPIO_REC);
}
int get_lid_switch(void)
{
return 1;
}

30
src/mainboard/google/hatch/chromeos.fmd
View File

@ -1,22 +1,20 @@
FLASH@0xfe000000 0x2000000 { FLASH@0xfe000000 0x2000000 {
SI_ALL@0x0 0x1000000 { SI_ALL@0x0 0x300000 {
SI_DESC@0x0 0x1000 SI_DESC@0x0 0x1000
SI_EC@0x1000 0x100000 SI_ME@0x1000 0x2ff000
SI_GBE@0x101000 0x2000
SI_ME@0x103000 0xefd000
} }
SI_BIOS@0x1000000 0x1000000 { SI_BIOS@0x1000000 0x1000000 {
RW_SECTION_A@0x0 0x280000 { RW_SECTION_A@0x0 0x300000 {
VBLOCK_A@0x0 0x10000 VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x26ffc0 FW_MAIN_A(CBFS)@0x10000 0x2effc0
RW_FWID_A@0x27ffc0 0x40 RW_FWID_A@0x2fffc0 0x40
} }
RW_SECTION_B@0x280000 0x280000 { RW_SECTION_B@0x300000 0x300000 {
VBLOCK_B@0x0 0x10000 VBLOCK_B@0x0 0x10000
FW_MAIN_B(CBFS)@0x10000 0x26ffc0 FW_MAIN_B(CBFS)@0x10000 0x2effc0
RW_FWID_B@0x27ffc0 0x40 RW_FWID_B@0x2fffc0 0x40
} }
RW_MISC@0x500000 0x30000 { RW_MISC@0x600000 0x30000 {
UNIFIED_MRC_CACHE@0x0 0x20000 { UNIFIED_MRC_CACHE@0x0 0x20000 {
RECOVERY_MRC_CACHE@0x0 0x10000 RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x10000 RW_MRC_CACHE@0x10000 0x10000
@ -29,17 +27,15 @@ FLASH@0xfe000000 0x2000000 {
RW_VPD@0x28000 0x2000 RW_VPD@0x28000 0x2000
RW_NVRAM@0x2a000 0x6000 RW_NVRAM@0x2a000 0x6000
} }
CONSOLE@0x530000 0x20000 RW_LEGACY(CBFS)@0x630000 0x5a0000
RW_LEGACY(CBFS)@0x550000 0x6b0000 WP_RO@0xbd0000 0x430000 {
WP_RO@0xc00000 0x400000 {
RO_VPD@0x0 0x4000 RO_VPD@0x0 0x4000
RO_UNUSED@0x4000 0xc000 RO_SECTION@0x4000 0x42c000 {
RO_SECTION@0x10000 0x3f0000 {
FMAP@0x0 0x800 FMAP@0x0 0x800
RO_FRID@0x800 0x40 RO_FRID@0x800 0x40
RO_FRID_PAD@0x840 0x7c0 RO_FRID_PAD@0x840 0x7c0
GBB@0x1000 0xef000 GBB@0x1000 0xef000
COREBOOT(CBFS)@0xf0000 0x300000 COREBOOT(CBFS)@0xf0000 0x33c000
} }
} }
} }

4
src/mainboard/google/hatch/variants/baseboard/gpio.c
View File

@ -29,6 +29,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
/* H1_PCH_INT_ODL */ /* H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT), PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT),
/* PCH_WP_OD */
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
/* EC_IN_RW_OD */
PAD_CFG_GPI(GPP_C22, NONE, DEEP),
}; };
const struct pad_config *__weak variant_gpio_table(size_t *num) const struct pad_config *__weak variant_gpio_table(size_t *num)

4
src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
View File

@ -18,4 +18,8 @@
#include <soc/gpio.h> #include <soc/gpio.h>
#define GPIO_EC_IN_RW GPP_C22
#define GPIO_PCH_WP GPP_C20
#endif /* BASEBOARD_GPIO_H */ #endif /* BASEBOARD_GPIO_H */

52
src/mainboard/google/hatch/variants/hatch/overridetree.cb
View File

@ -1,52 +0,0 @@
chip soc/intel/cannonlake
device domain 0 on
device pci 00.0 off end # Host Bridge
device pci 02.0 off end # Integrated Graphics Device
device pci 04.0 off end # SA Thermal device
device pci 12.0 off end # Thermal Subsystem
device pci 12.5 off end # UFS SCS
device pci 12.6 off end # GSPI #2
device pci 14.0 off end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.5 off end # SDCard
device pci 15.0 off end # I2C #0
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 16.0 off end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 off end # SATA
device pci 19.0 off end # I2C #4
device pci 19.1 off end # I2C #5
device pci 19.2 off end # UART #2
device pci 1a.0 off end # eMMC
device pci 1c.0 off end # PCI Express Port 1 (USB)
device pci 1c.1 off end # PCI Express Port 2 (USB)
device pci 1c.2 off end # PCI Express Port 3 (USB)
device pci 1c.3 off end # PCI Express Port 4 (USB)
device pci 1c.4 off end # PCI Express Port 5 (USB)
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 off end # PCI Express Port 9
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 off end # PCI Express Port 13 (x4)
device pci 1e.0 off end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1f.0 off end # LPC/eSPI
device pci 1f.1 off end # P2SB
device pci 1f.2 off end # Power Management Controller
device pci 1f.3 off end # Intel HDA
device pci 1f.4 off end # SMBus
device pci 1f.5 off end # PCH SPI
device pci 1f.6 off end # GbE
end
end