mb/google/hatch: Fixes to initial hatch mainboard checkin
Incorporating some feedback to initial hatch mainboard checking (CL:30169) that came in after the CL merged. Updated the chromeos.fmd with the following, * SI_ALL = 3MB * SI_BIOS = 16MB BUG=b:20914069 BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a -v Change-Id: I4e311c68873f10f71314e44d3a714639a06dbee8 Signed-off-by: Shelley Chen <shchen@google.com> Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/30296 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shelley Chen
Patrick Georgi
parent
74e0390e74
commit
6bb563f29c
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@ -23,10 +23,14 @@ if BOARD_GOOGLE_BASEBOARD_HATCH
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config CHROMEOS
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bool
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default y
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select GBB_FLAG_FORCE_DEV_SWITCH_ON
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select GBB_FLAG_FORCE_DEV_BOOT_USB
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select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
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select GBB_FLAG_FORCE_MANUAL_RECOVERY
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select HAS_RECOVERY_MRC_CACHE
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select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
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select VBOOT_LID_SWITCH
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config DEVICETREE
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string
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@ -68,10 +72,6 @@ config MAX_CPUS
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int
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default 8
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config OVERRIDE_DEVICETREE
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string
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default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_HATCH
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config TPM_TIS_ACPI_INTERRUPT
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int
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default 53 # GPE0_DW1_21 (GPP_C21)
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@ -29,29 +29,15 @@ void fill_lb_gpios(struct lb_gpios *gpios)
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{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
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{-1, ACTIVE_HIGH, 0, "power"},
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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{-1, ACTIVE_HIGH, 0, "EC in RW"},
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{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW),
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"EC in RW"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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static int cros_get_gpio_value(int type)
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int get_write_protect_state(void)
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{
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const struct cros_gpio *cros_gpios;
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size_t i, num_gpios = 0;
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cros_gpios = variant_cros_gpios(&num_gpios);
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for (i = 0; i < num_gpios; i++) {
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const struct cros_gpio *gpio = &cros_gpios[i];
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if (gpio->type == type) {
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int state = gpio_get(gpio->gpio_num);
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if (gpio->polarity == CROS_GPIO_ACTIVE_LOW)
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return !state;
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else
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return state;
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}
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}
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return 0;
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return gpio_get(GPIO_PCH_WP);
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}
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void mainboard_chromeos_acpi_generate(void)
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@ -63,18 +49,3 @@ void mainboard_chromeos_acpi_generate(void)
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chromeos_acpi_gpio_generate(cros_gpios, num_gpios);
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}
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int get_write_protect_state(void)
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{
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return cros_get_gpio_value(CROS_GPIO_WP);
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}
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int get_recovery_mode_switch(void)
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{
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return cros_get_gpio_value(CROS_GPIO_REC);
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}
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int get_lid_switch(void)
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{
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return 1;
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}
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@ -1,22 +1,20 @@
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FLASH@0xfe000000 0x2000000 {
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SI_ALL@0x0 0x1000000 {
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SI_ALL@0x0 0x300000 {
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SI_DESC@0x0 0x1000
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SI_EC@0x1000 0x100000
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SI_GBE@0x101000 0x2000
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SI_ME@0x103000 0xefd000
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SI_ME@0x1000 0x2ff000
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}
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SI_BIOS@0x1000000 0x1000000 {
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RW_SECTION_A@0x0 0x280000 {
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RW_SECTION_A@0x0 0x300000 {
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VBLOCK_A@0x0 0x10000
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FW_MAIN_A(CBFS)@0x10000 0x26ffc0
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RW_FWID_A@0x27ffc0 0x40
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FW_MAIN_A(CBFS)@0x10000 0x2effc0
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RW_FWID_A@0x2fffc0 0x40
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}
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RW_SECTION_B@0x280000 0x280000 {
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RW_SECTION_B@0x300000 0x300000 {
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VBLOCK_B@0x0 0x10000
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FW_MAIN_B(CBFS)@0x10000 0x26ffc0
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RW_FWID_B@0x27ffc0 0x40
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FW_MAIN_B(CBFS)@0x10000 0x2effc0
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RW_FWID_B@0x2fffc0 0x40
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}
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RW_MISC@0x500000 0x30000 {
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RW_MISC@0x600000 0x30000 {
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UNIFIED_MRC_CACHE@0x0 0x20000 {
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RECOVERY_MRC_CACHE@0x0 0x10000
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RW_MRC_CACHE@0x10000 0x10000
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@ -29,17 +27,15 @@ FLASH@0xfe000000 0x2000000 {
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RW_VPD@0x28000 0x2000
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RW_NVRAM@0x2a000 0x6000
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}
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CONSOLE@0x530000 0x20000
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RW_LEGACY(CBFS)@0x550000 0x6b0000
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WP_RO@0xc00000 0x400000 {
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RW_LEGACY(CBFS)@0x630000 0x5a0000
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WP_RO@0xbd0000 0x430000 {
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RO_VPD@0x0 0x4000
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RO_UNUSED@0x4000 0xc000
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RO_SECTION@0x10000 0x3f0000 {
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RO_SECTION@0x4000 0x42c000 {
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FMAP@0x0 0x800
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RO_FRID@0x800 0x40
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RO_FRID_PAD@0x840 0x7c0
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GBB@0x1000 0xef000
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COREBOOT(CBFS)@0xf0000 0x300000
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COREBOOT(CBFS)@0xf0000 0x33c000
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}
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}
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}
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@ -29,6 +29,10 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT),
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/* PCH_WP_OD */
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PAD_CFG_GPI(GPP_C20, NONE, DEEP),
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/* EC_IN_RW_OD */
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PAD_CFG_GPI(GPP_C22, NONE, DEEP),
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};
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const struct pad_config *__weak variant_gpio_table(size_t *num)
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@ -18,4 +18,8 @@
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#include <soc/gpio.h>
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#define GPIO_EC_IN_RW GPP_C22
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#define GPIO_PCH_WP GPP_C20
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#endif /* BASEBOARD_GPIO_H */
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@ -1,52 +0,0 @@
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chip soc/intel/cannonlake
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device domain 0 on
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device pci 00.0 off end # Host Bridge
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device pci 02.0 off end # Integrated Graphics Device
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device pci 04.0 off end # SA Thermal device
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device pci 12.0 off end # Thermal Subsystem
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device pci 12.5 off end # UFS SCS
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device pci 12.6 off end # GSPI #2
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device pci 14.0 off end # USB xHCI
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.5 off end # SDCard
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device pci 15.0 off end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 16.5 off end # Management Engine Interface 4
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device pci 17.0 off end # SATA
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device pci 19.0 off end # I2C #4
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device pci 19.1 off end # I2C #5
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device pci 19.2 off end # UART #2
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device pci 1a.0 off end # eMMC
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device pci 1c.0 off end # PCI Express Port 1 (USB)
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device pci 1c.1 off end # PCI Express Port 2 (USB)
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device pci 1c.2 off end # PCI Express Port 3 (USB)
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device pci 1c.3 off end # PCI Express Port 4 (USB)
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device pci 1c.4 off end # PCI Express Port 5 (USB)
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 off end # PCI Express Port 9
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device pci 1d.1 off end # PCI Express Port 10
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1d.4 off end # PCI Express Port 13 (x4)
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device pci 1e.0 off end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1f.0 off end # LPC/eSPI
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device pci 1f.1 off end # P2SB
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device pci 1f.2 off end # Power Management Controller
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device pci 1f.3 off end # Intel HDA
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device pci 1f.4 off end # SMBus
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device pci 1f.5 off end # PCH SPI
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device pci 1f.6 off end # GbE
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end
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end
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