GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Following patch adds support for the ACPI resume on Asus M2V-MX SE. The ACPI 

code just blinks the leds. The motherboard resources are use to reserve coreboot
used memory.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Rudolf Marek 2009-04-13 18:37:17 +00:00
parent 15bf50d820
commit 6bb6e03912
4 changed files with 37 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/asus/m2v-mx_se/Options.lb
View File

@ -49,6 +49,7 @@ uses CONFIG_LB_MEM_TOPK
uses HAVE_ACPI_TABLES uses HAVE_ACPI_TABLES
uses HAVE_MAINBOARD_RESOURCES uses HAVE_MAINBOARD_RESOURCES
uses HAVE_HIGH_TABLES uses HAVE_HIGH_TABLES
uses HAVE_ACPI_RESUME
uses HAVE_LOW_TABLES uses HAVE_LOW_TABLES
uses LB_CKS_RANGE_START uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END uses LB_CKS_RANGE_END
@ -116,6 +117,7 @@ default HAVE_ACPI_TABLES = 1
default HAVE_MAINBOARD_RESOURCES = 1 default HAVE_MAINBOARD_RESOURCES = 1
default HAVE_HIGH_TABLES = 1 default HAVE_HIGH_TABLES = 1
default HAVE_LOW_TABLES = 0 default HAVE_LOW_TABLES = 0
default HAVE_ACPI_RESUME = 1
# 1G memory hole # 1G memory hole
# bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000 # bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000
@ -157,9 +159,9 @@ default ROM_IMAGE_SIZE = 64 * 1024
default STACK_SIZE = 8 * 1024 default STACK_SIZE = 8 * 1024
default HEAP_SIZE = 256 * 1024 default HEAP_SIZE = 256 * 1024
# More 1M for pgtbl. # More 1M for pgtbl.
default CONFIG_LB_MEM_TOPK = 2048 default CONFIG_LB_MEM_TOPK = 32768
# to 1MB # to 1MB
default _RAMBASE = 0x100000 default _RAMBASE = 0x1F00000
# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE # default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default CONFIG_ROM_PAYLOAD = 1 default CONFIG_ROM_PAYLOAD = 1
default CC = "$(CROSS_COMPILE)gcc -m32" default CC = "$(CROSS_COMPILE)gcc -m32"

5
src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
View File

@ -97,14 +97,13 @@ void activate_spd_rom(const struct mem_controller *ctrl)
#define K8_4RANK_DIMM_SUPPORT 1 #define K8_4RANK_DIMM_SUPPORT 1
#include "southbridge/via/k8t890/k8t890_early_car.c"
#include "northbridge/amd/amdk8/amdk8.h" #include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/raminit_f.c"
#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/incoherent_ht.c"
#include "sdram/generic_sdram.c" #include "sdram/generic_sdram.c"
#include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/via/k8t890/k8t890_early_car.c"
#include "cpu/amd/car/copy_and_run.c" #include "cpu/amd/car/copy_and_run.c"
#include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"
@ -242,10 +241,12 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = struct sys_info *sysinfo =
(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
char *p; char *p;
u8 reg;
sio_init(); sio_init();
it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE); it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE);
it8712f_kill_watchdog(); it8712f_kill_watchdog();
it8712f_enable_3vsbsw();
uart_init(); uart_init();
console_init(); console_init();
enable_rom_decode(); enable_rom_decode();

23
src/mainboard/asus/m2v-mx_se/dsdt.asl
View File

@ -30,8 +30,24 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
* Any others would involve declaring the wake up methods. * Any others would involve declaring the wake up methods.
*/ */
Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
Name (\_S3, Package () { 0x01, 0x01, 0x00, 0x00 })
Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
/* blink a LED when entering the sleep (any type) */
Method (_PTS, 1, NotSerialized)
{
Store (0x1, \_SB.PCI0.ISA.LEDR)
}
/* cancel a LED blinking when waking from sleep (any type) */
Method (_WAK, 1, NotSerialized)
{
Store (0x0, \_SB.PCI0.ISA.LEDR)
/* wake OK */
Return(Package(0x02){0x00, 0x00})
}
/* Root of the bus hierarchy */ /* Root of the bus hierarchy */
Scope (\_SB) Scope (\_SB)
{ {
@ -160,6 +176,13 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
} }
Device (ISA) { Device (ISA) {
Name (_ADR, 0x00110000) Name (_ADR, 0x00110000)
OperationRegion (PCIC, PCI_Config, 0x0, 0xff)
Field (PCIC, ByteAcc, NoLock, Preserve)
{
Offset (0x94),
/* two LSB bits are blink rate */
LEDR, 2,
}
/* PS/2 keyboard (seems to be important for WinXP install) */ /* PS/2 keyboard (seems to be important for WinXP install) */
Device (KBD) Device (KBD)

6
src/mainboard/asus/m2v-mx_se/mainboard.c
View File

@ -33,6 +33,12 @@ int add_mainboard_resources(struct lb_memory *mem)
printk_debug("Adding high table area\n"); printk_debug("Adding high table area\n");
lb_add_memory_range(mem, LB_MEM_TABLE, lb_add_memory_range(mem, LB_MEM_TABLE,
high_tables_base, high_tables_size); high_tables_base, high_tables_size);
#endif
#if HAVE_ACPI_RESUME == 1
lb_add_memory_range(mem, LB_MEM_RESERVED,
_RAMBASE, ((CONFIG_LB_MEM_TOPK<<10) - _RAMBASE));
lb_add_memory_range(mem, LB_MEM_RESERVED,
DCACHE_RAM_BASE, DCACHE_RAM_SIZE);
#endif #endif
return 0; return 0;
} }