soc/intel/common/block: Add option to have subsystem_id in common pci driver

This patch ensures all Intel common PCI devices can
have subsystem ID programmed along with PCI resource
enabling (.enable_resources) as part of PCI enumeration
process.

TEST=Build and boot KBL/CNL/APL/GLK to ensure PCI
subsystem ID getting programmed.
Example:
Enabling resources...
PCI: 00:00.0 subsystem <- 8086/590c
PCI: 00:00.0 cmd <- 06
PCI: 00:02.0 subsystem <- 8086/591e

Change-Id: I46307b0db78c8864c85865bd0f3328d5141971be
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22768
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik 2017-12-07 14:55:51 +05:30
parent ffc790bc7f
commit 6bbc91a964
17 changed files with 38 additions and 12 deletions

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@ -502,6 +502,7 @@ static struct device_operations cse_ops = {
.read_resources = pci_dev_read_resources,
.enable_resources = pci_dev_enable_resources,
.init = pci_dev_init,
.ops_pci = &pci_dev_ops_pci,
};
static const unsigned short pci_device_ids[] = {

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@ -22,6 +22,7 @@ static struct device_operations dsp_dev_ops = {
.read_resources = &pci_dev_read_resources,
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.ops_pci = &pci_dev_ops_pci,
.scan_bus = &scan_static_bus,
};

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@ -99,6 +99,7 @@ static const struct device_operations graphics_ops = {
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = graphics_soc_init,
.ops_pci = &pci_dev_ops_pci,
.write_acpi_tables = graphics_soc_write_acpi_opregion,
};

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@ -172,6 +172,7 @@ static struct device_operations i2c_dev_ops = {
.enable_resources = &pci_dev_enable_resources,
.scan_bus = &scan_smbus,
.ops_i2c_bus = &i2c_bus_ops,
.ops_pci = &pci_dev_ops_pci,
.init = &lpss_i2c_dev_init,
.acpi_fill_ssdt_generator = &lpss_i2c_acpi_fill_ssdt,
};

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@ -96,6 +96,7 @@ static struct device_operations device_ops = {
.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
.init = lpc_init,
.scan_bus = scan_lpc_bus,
.ops_pci = &pci_dev_ops_pci,
};
static const unsigned short pci_device_ids[] = {

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@ -64,6 +64,7 @@ static void read_resources(struct device *dev)
static const struct device_operations device_ops = {
.read_resources = read_resources,
.set_resources = DEVICE_NOOP,
.ops_pci = &pci_dev_ops_pci,
};
static const unsigned short pci_device_ids[] = {

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@ -24,6 +24,8 @@
#define PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE 0x1003
/* Latency tolerance reporting, max snoop latency value 3.14ms */
#define PCIE_LTR_MAX_SNOOP_LATENCY_VALUE 0x1003
/* PCI-E Sub-System ID */
#define PCIE_SUBSYSTEM_VENDOR_ID 0x94
static void pch_pcie_init(struct device *dev)
{
@ -69,8 +71,16 @@ static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int offset)
PCIE_LTR_MAX_SNOOP_LATENCY_VALUE);
}
static void pcie_dev_set_subsystem(struct device *dev,
unsigned vendor, unsigned device)
{
pci_write_config32(dev, PCIE_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations pcie_ops = {
.set_L1_ss_latency = pcie_set_L1_ss_max_latency,
.set_subsystem = pcie_dev_set_subsystem,
};
static struct device_operations device_ops = {

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@ -99,6 +99,7 @@ static struct device_operations device_ops = {
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.init = &pmc_soc_init,
.ops_pci = &pci_dev_ops_pci,
.scan_bus = &scan_lpc_bus,
};

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@ -63,6 +63,7 @@ static struct device_operations sata_ops = {
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.final = sata_final,
.ops_pci = &pci_dev_ops_pci,
};
static const unsigned short pci_device_ids[] = {

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@ -61,6 +61,7 @@ static struct device_operations dev_ops = {
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
.acpi_fill_ssdt_generator = &sd_fill_ssdt,
#endif
.ops_pci = &pci_dev_ops_pci,
};
static const unsigned short pci_device_ids[] = {

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@ -83,6 +83,7 @@ static struct device_operations smbus_ops = {
.enable_resources = &pci_dev_enable_resources,
.scan_bus = &scan_smbus,
.init = &pch_smbus_init,
.ops_pci = &pci_dev_ops_pci,
.ops_smbus_bus = &lops_smbus_bus,
};

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@ -49,6 +49,7 @@ static struct device_operations spi_dev_ops = {
.enable_resources = &pci_dev_enable_resources,
.scan_bus = &scan_generic_bus,
.ops_spi_bus = &spi_bus_ops,
.ops_pci = &pci_dev_ops_pci,
};
static const unsigned short pci_device_ids[] = {

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@ -43,6 +43,7 @@ static const struct device_operations device_ops = {
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = soc_sram_init,
.ops_pci = &pci_dev_ops_pci,
};
static const unsigned short pci_device_ids[] = {

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@ -281,6 +281,7 @@ static struct device_operations systemagent_ops = {
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.init = soc_systemagent_init,
.ops_pci = &pci_dev_ops_pci,
};
static const unsigned short systemagent_ids[] = {

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@ -144,6 +144,7 @@ static struct device_operations device_ops = {
.read_resources = &pch_uart_read_resources,
.set_resources = &pci_dev_set_resources,
.enable_resources = &uart_common_enable_resources,
.ops_pci = &pci_dev_ops_pci,
};
static const unsigned short pci_device_ids[] = {

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@ -27,6 +27,7 @@ static struct device_operations usb_xdci_ops = {
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.init = soc_xdci_init,
.ops_pci = &pci_dev_ops_pci,
};
static const unsigned short pci_device_ids[] = {

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@ -27,6 +27,7 @@ static struct device_operations usb_xhci_ops = {
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.init = soc_xhci_init,
.ops_pci = &pci_dev_ops_pci,
};
static const unsigned short pci_device_ids[] = {