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util/amdfwtool: Deal with psp position in flash offset directly 

It is based on work by Arthur Heymans, 69852.

Get rid of the confusing "position index" and use the relative flash
offset as the Kconfig setting instead.

TEST=binary identical on amd/birman amd/majolica amd/gardenia
  amd/mayan amd/bilby amd/mandolin amd/chausie amd/pademelon
  pcengines/apu2
  google/skyrim google/guybrush google/zork google/kahlee google/myst
  (The test should be done with INCLUDE_CONFIG_FILE=n)

Change-Id: I26bde0b7c70efe9f5762109f431329ea7f95b7f2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Zheng Bao 2023-02-14 13:26:31 +08:00 committed by Felix Held
parent d0de6c2183
commit 6bc06983ed
23 changed files with 94 additions and 287 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/mainboard/amd/chausie/Kconfig
View File

@ -15,6 +15,8 @@ config BOARD_SPECIFIC_OPTIONS
select PCIEXP_COMMON_CLOCK
select PCIEXP_L1_SUB_STATE
select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD
select AMD_FWM_POSITION_C20000_DEFAULT if CHROMEOS
select AMD_FWM_POSITION_820000_DEFAULT if !CHROMEOS
select SOC_AMD_COMMON_BLOCK_SIMNOW_SUPPORTED
config FMDFILE
@ -27,13 +29,6 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER
default "CHAUSIE"
config AMD_FWM_POSITION_INDEX
int
default 3 if CHROMEOS
default 4
help
TODO: might need to be adapted for better placement of files in cbfs
config CHAUSIE_HAVE_MCHP_FW
bool "Have Microchip EC firmware?"
default n

9
src/mainboard/amd/majolica/Kconfig
View File

@ -10,6 +10,8 @@ config BOARD_SPECIFIC_OPTIONS
select AMD_SOC_CONSOLE_UART
select PSP_INIT_ESPI
select MAINBOARD_HAS_CHROMEOS
select AMD_FWM_POSITION_C20000_DEFAULT if CHROMEOS
select AMD_FWM_POSITION_820000_DEFAULT if !CHROMEOS
config FMDFILE
default "src/mainboard/amd/majolica/chromeos.fmd" if CHROMEOS
@ -21,13 +23,6 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER
default "MAJOLICA"
config AMD_FWM_POSITION_INDEX
int
default 3 if CHROMEOS
default 4
help
TODO: might need to be adapted for better placement of files in cbfs
config MAJOLICA_HAVE_MCHP_FW
bool "Have Microchip EC firmware?"
default n

9
src/mainboard/amd/mandolin/Kconfig
View File

@ -12,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_RESUME
select DRIVERS_UART_ACPI
select AMD_SOC_CONSOLE_UART if !AMD_LPC_DEBUG_CARD
select AMD_FWM_POSITION_420000_DEFAULT if BOARD_AMD_MANDOLIN
select AMD_FWM_POSITION_820000_DEFAULT if BOARD_AMD_CEREME
config FMDFILE
default "src/mainboard/amd/mandolin/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
@ -67,13 +69,6 @@ config ONBOARD_VGA_IS_PRIMARY
bool
default y
config AMD_FWM_POSITION_INDEX
int
default 3 if BOARD_AMD_MANDOLIN
default 4 if BOARD_AMD_CEREME
help
TODO: might need to be adapted for better placement of files in cbfs
config MANDOLIN_HAVE_MCHP_FW
bool "Have Microchip EC firmware?"
default n

7
src/mainboard/google/guybrush/Kconfig
View File

@ -49,6 +49,7 @@ config BOARD_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL
select SYSTEM_TYPE_LAPTOP
select TPM_GOOGLE_CR50
select AMD_FWM_POSITION_C20000_DEFAULT
config VBOOT
select EC_GOOGLE_CHROMEEC_SWITCHES
@ -81,12 +82,6 @@ config MAINBOARD_PART_NUMBER
default "Nipperkin" if BOARD_GOOGLE_NIPPERKIN
default "Dewatt" if BOARD_GOOGLE_DEWATT
config AMD_FWM_POSITION_INDEX
int
default 3
help
TODO: might need to be adapted for better placement of files in cbfs
config DRIVER_TPM_I2C_BUS
hex
default 0x03

5
src/mainboard/google/kahlee/Kconfig
View File

@ -35,6 +35,7 @@ config BOARD_GOOGLE_BASEBOARD_KAHLEE
select HAVE_EM100_SUPPORT
select SYSTEM_TYPE_LAPTOP
select TPM_GOOGLE_CR50
select AMD_FWM_POSITION_F20000_DEFAULT
if BOARD_GOOGLE_BASEBOARD_KAHLEE
@ -104,10 +105,6 @@ config VBOOT_VBNV_OFFSET
config CHROMEOS
select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE
config AMD_FWM_POSITION_INDEX
int
default 1
config DRIVER_TPM_I2C_BUS
hex
default 0x01

5
src/mainboard/google/skyrim/Kconfig
View File

@ -5,10 +5,6 @@ config BOARD_GOOGLE_BASEBOARD_SKYRIM
if BOARD_GOOGLE_BASEBOARD_SKYRIM
config AMD_FWM_POSITION_INDEX
int
default 3
config BOARD_SPECIFIC_OPTIONS
def_bool y
select ACPI_S1_NOT_SUPPORTED
@ -49,6 +45,7 @@ config BOARD_SPECIFIC_OPTIONS
select PCIEXP_CLK_PM
select PCIEXP_COMMON_CLOCK
select PCIEXP_L1_SUB_STATE
select AMD_FWM_POSITION_C20000_DEFAULT
config DEVICETREE
default "variants/baseboard/devicetree.cb"

5
src/mainboard/google/zork/Kconfig
View File

@ -51,6 +51,7 @@ config BOARD_SPECIFIC_OPTIONS
select DRIVERS_USB_ACPI
select DRIVERS_UART_ACPI
select DRIVERS_GENERIC_BAYHUB_LV2
select AMD_FWM_POSITION_E20000_DEFAULT
config ELOG_BOOT_COUNT_CMOS_OFFSET
int
@ -126,10 +127,6 @@ config CHROMEOS
# Use default libpayload config
select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE
config AMD_FWM_POSITION_INDEX
int
default 2
config DRIVER_TPM_I2C_BUS
hex
default 0x03

33
src/soc/amd/cezanne/Kconfig
View File

@ -322,39 +322,6 @@ config DISABLE_KEYBOARD_RESET_PIN
menu "PSP Configuration Options"
config AMD_FWM_POSITION_INDEX
int "Firmware Directory Table location (0 to 5)"
range 0 5
default 0 if BOARD_ROMSIZE_KB_512
default 1 if BOARD_ROMSIZE_KB_1024
default 2 if BOARD_ROMSIZE_KB_2048
default 3 if BOARD_ROMSIZE_KB_4096
default 4 if BOARD_ROMSIZE_KB_8192
default 5 if BOARD_ROMSIZE_KB_16384
help
Typically this is calculated by the ROM size, but there may
be situations where you want to put the firmware directory
table in a different location.
0: 512 KB - 0xFFFA0000
1: 1 MB - 0xFFF20000
2: 2 MB - 0xFFE20000
3: 4 MB - 0xFFC20000
4: 8 MB - 0xFF820000
5: 16 MB - 0xFF020000
comment "AMD Firmware Directory Table set to location for 512KB ROM"
depends on AMD_FWM_POSITION_INDEX = 0
comment "AMD Firmware Directory Table set to location for 1MB ROM"
depends on AMD_FWM_POSITION_INDEX = 1
comment "AMD Firmware Directory Table set to location for 2MB ROM"
depends on AMD_FWM_POSITION_INDEX = 2
comment "AMD Firmware Directory Table set to location for 4MB ROM"
depends on AMD_FWM_POSITION_INDEX = 3
comment "AMD Firmware Directory Table set to location for 8MB ROM"
depends on AMD_FWM_POSITION_INDEX = 4
comment "AMD Firmware Directory Table set to location for 16MB ROM"
depends on AMD_FWM_POSITION_INDEX = 5
config AMDFW_CONFIG_FILE
string
default "src/soc/amd/cezanne/fw.cfg"

11
src/soc/amd/cezanne/Makefile.inc
View File

@ -40,21 +40,12 @@ CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/cezanne
CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common
# ROMSIG Normally At ROMBASE + 0x20000
# Overridden by CONFIG_AMD_FWM_POSITION_INDEX
# +-----------+---------------+----------------+------------+
# |0x55AA55AA | | | |
# +-----------+---------------+----------------+------------+
# | | PSPDIR ADDR | BIOSDIR ADDR |
# +-----------+---------------+----------------+
$(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\
$(error Invalid AMD firmware position index. Check if the board sets a valid ROM size))
CEZANNE_FWM_POSITION=$(call int-add, \
$(call int-subtract, 0xffffffff \
$(call int-shift-left, \
0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1)
# 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes
# Building the cbfs image will fail if the offset isn't large enough
AMD_FW_AB_POSITION := 0x40
@ -222,7 +213,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
$(OPT_APOB_NV_BASE) \
$(OPT_VERSTAGE_FILE) \
$(OPT_VERSTAGE_SIG_FILE) \
--location $(call _tohex,$(CEZANNE_FWM_POSITION)) \
--location $(CONFIG_AMD_FWM_POSITION) \
--multilevel \
--output $@

5
src/soc/amd/common/Makefile.inc
View File

@ -47,9 +47,8 @@ $(objcbfs)/bootblock.bin: $(obj)/amdfw.rom
add_bootblock = \
$(CBFSTOOL) $(1) add -f $(2) -n apu/amdfw -t amdfw \
-b $(call int-add, \
$(call int-subtract, 0xffffffff \
$(call int-shift-left, \
0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1)
$(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 1 $(CONFIG_AMD_FWM_POSITION))
endif # ifeq ($(CONFIG_RESET_VECTOR_IN_RAM),y)
ifeq ($(CONFIG_VBOOT_GSCVD),y)

2
src/soc/amd/common/block/include/amdblocks/psp_efs.h
View File

@ -6,7 +6,7 @@
#include <types.h>
#define EFS_OFFSET (CONFIG_ROM_SIZE - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX) + 0x20000)
#define EFS_OFFSET CONFIG_AMD_FWM_POSITION
#define EMBEDDED_FW_SIGNATURE 0x55aa55aa

68
src/soc/amd/common/block/psp/Kconfig
View File

@ -55,3 +55,71 @@ config PSP_INCLUDES_HSP
default n
help
Select this config to indicate SoC includes Hardware Security Processor(HSP).
config AMD_FWM_POSITION_20000_DEFAULT
bool "0x20000"
config AMD_FWM_POSITION_420000_DEFAULT
bool "0x420000"
config AMD_FWM_POSITION_820000_DEFAULT
bool "0x820000"
config AMD_FWM_POSITION_C20000_DEFAULT
bool "0xC20000"
config AMD_FWM_POSITION_E20000_DEFAULT
bool "0xE20000"
config AMD_FWM_POSITION_F20000_DEFAULT
bool "0xF20000"
config AMD_FWM_POSITION_FA0000_DEFAULT
bool "0xFA0000"
choice AMD_FWM_POSITION_CHOICE
prompt "AMD FW position"
default AMD_FWM_POSITION_420000 if AMD_FWM_POSITION_420000_DEFAULT
default AMD_FWM_POSITION_820000 if AMD_FWM_POSITION_820000_DEFAULT
default AMD_FWM_POSITION_C20000 if AMD_FWM_POSITION_C20000_DEFAULT
default AMD_FWM_POSITION_E20000 if AMD_FWM_POSITION_E20000_DEFAULT
default AMD_FWM_POSITION_F20000 if AMD_FWM_POSITION_F20000_DEFAULT
default AMD_FWM_POSITION_FA0000 if AMD_FWM_POSITION_FA0000_DEFAULT
default AMD_FWM_POSITION_20000
help
Set the position on flash offset where the AMD FW needs to be.
This position is relative to a 16MB flash window. If the flash
size is smaller than 16MB it gets mapped at the top of that window.
config AMD_FWM_POSITION_20000
bool "0x20000"
config AMD_FWM_POSITION_420000
bool "0x420000"
config AMD_FWM_POSITION_820000
bool "0x820000"
config AMD_FWM_POSITION_C20000
bool "0xC20000"
config AMD_FWM_POSITION_E20000
bool "0xE20000"
config AMD_FWM_POSITION_F20000
bool "0xF20000"
config AMD_FWM_POSITION_FA0000
bool "0xFA0000"
endchoice
config AMD_FWM_POSITION
hex
default 0x20000 if AMD_FWM_POSITION_20000
default 0x420000 if AMD_FWM_POSITION_420000
default 0x820000 if AMD_FWM_POSITION_820000
default 0xc20000 if AMD_FWM_POSITION_C20000
default 0xe20000 if AMD_FWM_POSITION_E20000
default 0xf20000 if AMD_FWM_POSITION_F20000
default 0xfa0000 if AMD_FWM_POSITION_FA0000

33
src/soc/amd/glinda/Kconfig
View File

@ -300,39 +300,6 @@ config DISABLE_KEYBOARD_RESET_PIN
menu "PSP Configuration Options"
config AMD_FWM_POSITION_INDEX
int "Firmware Directory Table location (0 to 5)"
range 0 5
default 0 if BOARD_ROMSIZE_KB_512
default 1 if BOARD_ROMSIZE_KB_1024
default 2 if BOARD_ROMSIZE_KB_2048
default 3 if BOARD_ROMSIZE_KB_4096
default 4 if BOARD_ROMSIZE_KB_8192
default 5 if BOARD_ROMSIZE_KB_16384
help
Typically this is calculated by the ROM size, but there may
be situations where you want to put the firmware directory
table in a different location.
0: 512 KB - 0xFFFA0000
1: 1 MB - 0xFFF20000
2: 2 MB - 0xFFE20000
3: 4 MB - 0xFFC20000
4: 8 MB - 0xFF820000
5: 16 MB - 0xFF020000
comment "AMD Firmware Directory Table set to location for 512KB ROM"
depends on AMD_FWM_POSITION_INDEX = 0
comment "AMD Firmware Directory Table set to location for 1MB ROM"
depends on AMD_FWM_POSITION_INDEX = 1
comment "AMD Firmware Directory Table set to location for 2MB ROM"
depends on AMD_FWM_POSITION_INDEX = 2
comment "AMD Firmware Directory Table set to location for 4MB ROM"
depends on AMD_FWM_POSITION_INDEX = 3
comment "AMD Firmware Directory Table set to location for 8MB ROM"
depends on AMD_FWM_POSITION_INDEX = 4
comment "AMD Firmware Directory Table set to location for 16MB ROM"
depends on AMD_FWM_POSITION_INDEX = 5
config AMDFW_CONFIG_FILE
string "AMD PSP Firmware config file"
default "src/soc/amd/glinda/fw.cfg"

9
src/soc/amd/glinda/Makefile.inc
View File

@ -44,19 +44,12 @@ CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/glinda
CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common
# ROMSIG Normally At ROMBASE + 0x20000
# Overridden by CONFIG_AMD_FWM_POSITION_INDEX
# +-----------+---------------+----------------+------------+
# |0x55AA55AA | | | |
# +-----------+---------------+----------------+------------+
# | | PSPDIR ADDR | BIOSDIR ADDR |
# +-----------+---------------+----------------+
$(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\
$(error Invalid AMD firmware position index. Check if the board sets a valid ROM size))
# Fixed EFS location
GLINDA_FWM_POSITION=0xff020000
# 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes
# Building the cbfs image will fail if the offset isn't large enough
AMD_FW_AB_POSITION := 0x40
@ -240,7 +233,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
$(OPT_VERSTAGE_FILE) \
$(OPT_VERSTAGE_SIG_FILE) \
$(OPT_SPL_TABLE_FILE) \
--location $(call _tohex,$(GLINDA_FWM_POSITION)) \
--location $(CONFIG_AMD_FWM_POSITION) \
--output $@
$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)

33
src/soc/amd/mendocino/Kconfig
View File

@ -342,39 +342,6 @@ config FEATURE_TABLET_MODE_DPTC
menu "PSP Configuration Options"
config AMD_FWM_POSITION_INDEX
int "Firmware Directory Table location (0 to 5)"
range 0 5
default 0 if BOARD_ROMSIZE_KB_512
default 1 if BOARD_ROMSIZE_KB_1024
default 2 if BOARD_ROMSIZE_KB_2048
default 3 if BOARD_ROMSIZE_KB_4096
default 4 if BOARD_ROMSIZE_KB_8192
default 5 if BOARD_ROMSIZE_KB_16384
help
Typically this is calculated by the ROM size, but there may
be situations where you want to put the firmware directory
table in a different location.
0: 512 KB - 0xFFFA0000
1: 1 MB - 0xFFF20000
2: 2 MB - 0xFFE20000
3: 4 MB - 0xFFC20000
4: 8 MB - 0xFF820000
5: 16 MB - 0xFF020000
comment "AMD Firmware Directory Table set to location for 512KB ROM"
depends on AMD_FWM_POSITION_INDEX = 0
comment "AMD Firmware Directory Table set to location for 1MB ROM"
depends on AMD_FWM_POSITION_INDEX = 1
comment "AMD Firmware Directory Table set to location for 2MB ROM"
depends on AMD_FWM_POSITION_INDEX = 2
comment "AMD Firmware Directory Table set to location for 4MB ROM"
depends on AMD_FWM_POSITION_INDEX = 3
comment "AMD Firmware Directory Table set to location for 8MB ROM"
depends on AMD_FWM_POSITION_INDEX = 4
comment "AMD Firmware Directory Table set to location for 16MB ROM"
depends on AMD_FWM_POSITION_INDEX = 5
config AMDFW_CONFIG_FILE
string "AMD PSP Firmware config file"
default "src/soc/amd/mendocino/fw.cfg"

11
src/soc/amd/mendocino/Makefile.inc
View File

@ -43,21 +43,12 @@ CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/mendocino
CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common
# ROMSIG Normally At ROMBASE + 0x20000
# Overridden by CONFIG_AMD_FWM_POSITION_INDEX
# +-----------+---------------+----------------+------------+
# |0x55AA55AA | | | |
# +-----------+---------------+----------------+------------+
# | | PSPDIR ADDR | BIOSDIR ADDR |
# +-----------+---------------+----------------+
$(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\
$(error Invalid AMD firmware position index. Check if the board sets a valid ROM size))
MENDOCINO_FWM_POSITION=$(call int-add, \
$(call int-subtract, 0xffffffff \
$(call int-shift-left, \
0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1)
# 0x80 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes
# Building the cbfs image will fail if the offset isn't large enough
AMD_FW_AB_POSITION := 0x80
@ -265,7 +256,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
$(OPT_VERSTAGE_SIG_FILE) \
$(OPT_SPL_TABLE_FILE) \
$(OPT_MANIFEST) \
--location $(call _tohex,$(MENDOCINO_FWM_POSITION)) \
--location $(CONFIG_AMD_FWM_POSITION) \
--output $@
ifeq ($(CONFIG_CBFS_VERIFICATION)$(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK),yy)

17
src/soc/amd/phoenix/Kconfig
View File

@ -312,23 +312,6 @@ config DISABLE_KEYBOARD_RESET_PIN
menu "PSP Configuration Options"
config AMD_FWM_POSITION_INDEX
int
default 5
comment "AMD Firmware Directory Table set to location for 512KB ROM"
depends on AMD_FWM_POSITION_INDEX = 0
comment "AMD Firmware Directory Table set to location for 1MB ROM"
depends on AMD_FWM_POSITION_INDEX = 1
comment "AMD Firmware Directory Table set to location for 2MB ROM"
depends on AMD_FWM_POSITION_INDEX = 2
comment "AMD Firmware Directory Table set to location for 4MB ROM"
depends on AMD_FWM_POSITION_INDEX = 3
comment "AMD Firmware Directory Table set to location for 8MB ROM"
depends on AMD_FWM_POSITION_INDEX = 4
comment "AMD Firmware Directory Table set to location for 16MB ROM"
depends on AMD_FWM_POSITION_INDEX = 5
config AMDFW_CONFIG_FILE
string "AMD PSP Firmware config file"
default "src/soc/amd/phoenix/fw.cfg"

9
src/soc/amd/phoenix/Makefile.inc
View File

@ -47,19 +47,12 @@ CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/phoenix
CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common
# ROMSIG Normally At ROMBASE + 0x20000
# Overridden by CONFIG_AMD_FWM_POSITION_INDEX
# +-----------+---------------+----------------+------------+
# |0x55AA55AA | | | |
# +-----------+---------------+----------------+------------+
# | | PSPDIR ADDR | BIOSDIR ADDR |
# +-----------+---------------+----------------+
$(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\
$(error Invalid AMD firmware position index. Check if the board sets a valid ROM size))
# Fixed EFS location
PHOENIX_FWM_POSITION=0xff020000
# 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes
# Building the cbfs image will fail if the offset isn't large enough
AMD_FW_AB_POSITION := 0x40
@ -269,7 +262,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
$(OPT_VERSTAGE_SIG_FILE) \
$(OPT_SPL_TABLE_FILE) \
$(OPT_MANIFEST) \
--location $(call _tohex,$(PHOENIX_FWM_POSITION)) \
--location $(CONFIG_AMD_FWM_POSITION) \
--output $@
ifeq ($(CONFIG_AMDFW_SPLIT),y)

33
src/soc/amd/picasso/Kconfig
View File

@ -347,39 +347,6 @@ config FSP_TEMP_RAM_SIZE
menu "PSP Configuration Options"
config AMD_FWM_POSITION_INDEX
int "Firmware Directory Table location (0 to 5)"
range 0 5
default 0 if BOARD_ROMSIZE_KB_512
default 1 if BOARD_ROMSIZE_KB_1024
default 2 if BOARD_ROMSIZE_KB_2048
default 3 if BOARD_ROMSIZE_KB_4096
default 4 if BOARD_ROMSIZE_KB_8192
default 5 if BOARD_ROMSIZE_KB_16384
help
Typically this is calculated by the ROM size, but there may
be situations where you want to put the firmware directory
table in a different location.
0: 512 KB - 0xFFFA0000
1: 1 MB - 0xFFF20000
2: 2 MB - 0xFFE20000
3: 4 MB - 0xFFC20000
4: 8 MB - 0xFF820000
5: 16 MB - 0xFF020000
comment "AMD Firmware Directory Table set to location for 512KB ROM"
depends on AMD_FWM_POSITION_INDEX = 0
comment "AMD Firmware Directory Table set to location for 1MB ROM"
depends on AMD_FWM_POSITION_INDEX = 1
comment "AMD Firmware Directory Table set to location for 2MB ROM"
depends on AMD_FWM_POSITION_INDEX = 2
comment "AMD Firmware Directory Table set to location for 4MB ROM"
depends on AMD_FWM_POSITION_INDEX = 3
comment "AMD Firmware Directory Table set to location for 8MB ROM"
depends on AMD_FWM_POSITION_INDEX = 4
comment "AMD Firmware Directory Table set to location for 16MB ROM"
depends on AMD_FWM_POSITION_INDEX = 5
config AMDFW_CONFIG_FILE
string
default "src/soc/amd/picasso/fw.cfg"

11
src/soc/amd/picasso/Makefile.inc
View File

@ -46,21 +46,12 @@ CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/picasso/include
CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common
# ROMSIG Normally At ROMBASE + 0x20000
# Overridden by CONFIG_AMD_FWM_POSITION_INDEX
# +-----------+---------------+----------------+------------+
# |0x55AA55AA | | | |
# +-----------+---------------+----------------+------------+
# | | PSPDIR ADDR | BIOSDIR ADDR |
# +-----------+---------------+----------------+
$(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\
$(error Invalid AMD firmware position index. Check if the board sets a valid ROM size))
PICASSO_FWM_POSITION=$(call int-add, \
$(call int-subtract, 0xffffffff \
$(call int-shift-left, \
0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1)
# 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes
# Building the cbfs image will fail if the offset isn't large enough
AMD_FW_AB_POSITION := 0x40
@ -240,7 +231,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
$(OPT_APOB0_NV_BASE) \
$(OPT_VERSTAGE_FILE) \
$(OPT_VERSTAGE_SIG_FILE) \
--location $(call _tohex,$(PICASSO_FWM_POSITION)) \
--location $(CONFIG_AMD_FWM_POSITION) \
--output $@
$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)

33
src/soc/amd/stoneyridge/Kconfig
View File

@ -322,39 +322,6 @@ config AMDFW_OUTSIDE_CBFS
option to manually attach the generated amdfw.rom outside of
cbfs. The location is selected by the FWM position.
config AMD_FWM_POSITION_INDEX
int "Firmware Directory Table location (0 to 5)"
range 0 5
default 0 if BOARD_ROMSIZE_KB_512
default 1 if BOARD_ROMSIZE_KB_1024
default 2 if BOARD_ROMSIZE_KB_2048
default 3 if BOARD_ROMSIZE_KB_4096
default 4 if BOARD_ROMSIZE_KB_8192
default 5 if BOARD_ROMSIZE_KB_16384
help
Typically this is calculated by the ROM size, but there may
be situations where you want to put the firmware directory
table in a different location.
0: 512 KB - 0xFFFA0000
1: 1 MB - 0xFFF20000
2: 2 MB - 0xFFE20000
3: 4 MB - 0xFFC20000
4: 8 MB - 0xFF820000
5: 16 MB - 0xFF020000
comment "AMD Firmware Directory Table set to location for 512KB ROM"
depends on AMD_FWM_POSITION_INDEX = 0
comment "AMD Firmware Directory Table set to location for 1MB ROM"
depends on AMD_FWM_POSITION_INDEX = 1
comment "AMD Firmware Directory Table set to location for 2MB ROM"
depends on AMD_FWM_POSITION_INDEX = 2
comment "AMD Firmware Directory Table set to location for 4MB ROM"
depends on AMD_FWM_POSITION_INDEX = 3
comment "AMD Firmware Directory Table set to location for 8MB ROM"
depends on AMD_FWM_POSITION_INDEX = 4
comment "AMD Firmware Directory Table set to location for 16MB ROM"
depends on AMD_FWM_POSITION_INDEX = 5
config DIMM_SPD_SIZE
default 512 # DDR4

22
src/soc/amd/stoneyridge/Makefile.inc
View File

@ -64,7 +64,6 @@ CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include
CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/acpi
# ROMSIG Normally At ROMBASE + 0x20000
# Overridden by CONFIG_AMD_FWM_POSITION_INDEX
# +-----------+---------------+----------------+------------+
# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM |
# +-----------+---------------+----------------+------------+
@ -72,11 +71,6 @@ CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/acpi
# +-----------+
#
# EC ROM should be 64K aligned.
STONEYRIDGE_FWM_POSITION=$(call int-add, \
$(call int-subtract, 0xffffffff \
$(call int-shift-left, \
0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1)
### 0
FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}')
@ -138,26 +132,24 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \
$(OPT_DEBUG_AMDFWTOOL) \
--config $(CONFIG_AMDFW_CONFIG_FILE) \
--flashsize $(CONFIG_ROM_SIZE) \
--location $(call _tohex,$(STONEYRIDGE_FWM_POSITION)) \
--location $(CONFIG_AMD_FWM_POSITION) \
--output $@
ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
# Calculate firmware position inside the ROM
STONEYRIDGE_FWM_ROM_POSITION=$(call int-add, \
$(call int-subtract, $(CONFIG_ROM_SIZE) \
$(call int-shift-left, \
0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000)
$(call add_intermediate, add_amdfw, $(obj)/amdfw.rom)
printf " DD Adding AMD Firmware at ROM offset 0x%x\n" \
"$(STONEYRIDGE_FWM_ROM_POSITION)"
"$(CONFIG_AMD_FWM_POSITION)"
dd if=$(obj)/amdfw.rom \
of=$< conv=notrunc bs=1 \
seek=$(STONEYRIDGE_FWM_ROM_POSITION) >/dev/null 2>&1
seek=$(CONFIG_AMD_FWM_POSITION) >/dev/null 2>&1
else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
STONEYRIDGE_FWM_POSITION=$(call int-add, \
$(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) \
1 \
$(CONFIG_AMD_FWM_POSITION))
cbfs-files-y += apu/amdfw
apu/amdfw-file := $(obj)/amdfw.rom
apu/amdfw-position := $(STONEYRIDGE_FWM_POSITION)

2
src/soc/amd/stoneyridge/fch.c
View File

@ -151,7 +151,7 @@ static void set_sb_gnvs(struct global_nvs *gnvs)
uintptr_t fwaddr;
size_t fwsize;
amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX);
amdfw_rom = 4ull * GiB - CONFIG_ROM_SIZE + CONFIG_AMD_FWM_POSITION;
xhci_fw = read32p(amdfw_rom + XHCI_FW_SIG_OFFSET);
fwaddr = 2 + read16p(xhci_fw + XHCI_FW_ADDR_OFFSET + XHCI_FW_BOOTRAM_SIZE);