GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/supermicro/x11ssm-f: enable AER for PCIe root ports 

Follow vendor and enable Advanced Error Reporting for PCIe root ports.
This enabled the Linux AER driver, which handles PCIe error conditions.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I9d9b5afca0ca891e2812445db1d42a46ba16199e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48369
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner 2020-12-05 23:00:03 +01:00
parent 0bae5a72c5
commit 6bc1296cbd
1 changed files with 5 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
View File

@ -54,16 +54,19 @@ chip soc/intel/skylake
device pci 1c.0 on # PCH PCIe Port 1 / PCIe Slot 4 (JPCIE4)
register "PcieRpEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpAdvancedErrorReporting[0]" = "1"
smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
end
device pci 1c.4 on # PCH PCIe Port 5 / PCIe Slot 5 (JPCIE5)
register "PcieRpEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpAdvancedErrorReporting[4]" = "1"
smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
end
device pci 1d.0 on # PCH PCIe Port 9
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpAdvancedErrorReporting[8]" = "1"
device pci 00.0 on # GbE 1
subsystemid 0x15d9 0x1533
end
@ -71,6 +74,7 @@ chip soc/intel/skylake
device pci 1d.1 on # PCH PCIe Port 10
register "PcieRpEnable[9]" = "1"
register "PcieRpLtrEnable[9]" = "1"
register "PcieRpAdvancedErrorReporting[9]" = "1"
device pci 00.0 on # GbE 2
subsystemid 0x15d9 0x1533
end
@ -78,6 +82,7 @@ chip soc/intel/skylake
device pci 1d.2 on # PCH PCIe Port 11
register "PcieRpEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpAdvancedErrorReporting[10]" = "1"
device pci 00.0 on # Aspeed PCI Bridge
device pci 00.0 on end # Aspeed 2400 VGA
end