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northbridge/amd/amdmct/mct_ddr3: Remove commented code 

Change-Id: I2a52db28353f8575d11218af936b4a233fd05f77
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16889
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS 2016-10-05 18:30:58 +02:00 committed by Martin Roth
parent 59840d1dee
commit 6bc3b96831
2 changed files with 0 additions and 33 deletions
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16
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
View File

@ -34,8 +34,6 @@
#include <reset.h>
// #define DEBUG_DIMM_SPD 1
static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstatA);
static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
@ -2829,17 +2827,6 @@ restartinit:
* speed is the same as the speed used in the previous boot.
* How to get the desired speed at this point in the code?
*/
#if 0
for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
struct DCTStatStruc *pDCTstat;
pDCTstat = pDCTstatA + Node;
if (pDCTstat->NodePresent) {
if (pDCTstat->spd_data.nvram_memclk[0] != pDCTstat->DIMMAutoSpeed)
allow_config_restore = 0;
}
}
#endif
printk(BIOS_DEBUG, "mctAutoInitMCT_D: DQSTiming_D\n");
DQSTiming_D(pMCTstat, pDCTstatA, allow_config_restore); /* Get Receiver Enable and DQS signal timing*/
@ -3623,7 +3610,6 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
}
retry_dqs_training_and_levelization:
// nv_DQSTrainCTL = mctGet_NVbits(NV_DQSTrainCTL);
nv_DQSTrainCTL = !allow_config_restore;
mct_BeforeDQSTrain_D(pMCTstat, pDCTstatA);
@ -3662,8 +3648,6 @@ retry_dqs_training_and_levelization:
mct_WriteLevelization_HW(pMCTstat, pDCTstatA, SecondPass);
if (is_fam15h()) {
/* Receiver Enable Training Pass 2 */
// TrainReceiverEn_D(pMCTstat, pDCTstatA, SecondPass);
/* TODO:
* Determine why running TrainReceiverEn_D in SecondPass

17
src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
View File

@ -951,11 +951,6 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat,
* This does not seem to be needed, and has a tendency to lock up the
* boot process while attempting to write the test pattern.
*/
#if 0
SetUpperFSbase(TestAddr0);
WriteLNTestPattern(TestAddr0 << 8, (uint8_t *)TestPattern2_D, 1);
mct_Read1LTestPattern_D(pMCTstat, pDCTstat, TestAddr0);
#endif
}
MaxDelay_CH[Channel] = CTLRMaxDelay;
}
@ -1087,7 +1082,6 @@ static void generate_dram_receiver_enable_training_pattern_fam15(struct MCTStatS
/* 2.10.5.8.6.1.2 */
dword = Get_NB32_DCT(dev, dct, 0x270);
dword &= ~(0x7ffff); /* DataPrbsSeed = 55555 */
// dword |= (0x55555);
dword |= (0x44443); /* Use AGESA seed */
Set_NB32_DCT(dev, dct, 0x270, dword);
@ -1097,17 +1091,6 @@ static void generate_dram_receiver_enable_training_pattern_fam15(struct MCTStatS
dword |= 192;
Set_NB32_DCT(dev, dct, 0x260, dword);
#if 0
/* TODO: This applies to Fam15h model 10h and above only */
/* Program Bubble Count and CmdStreamLen */
dword = Get_NB32_DCT(dev, dct, 0x25c);
dword &= ~(0x3ff << 12); /* BubbleCnt = 0 */
dword &= ~(0x3ff << 22); /* BubbleCnt2 = 0 */
dword &= ~(0xff); /* CmdStreamLen = 1 */
dword |= 0x1;
Set_NB32_DCT(dev, dct, 0x25c, dword);
#endif
/* Configure Target A */
dword = Get_NB32_DCT(dev, dct, 0x254);
dword &= ~(0x7 << 24); /* TgtChipSelect = Receiver */