soc/intel/skylake: Clean up SD GPIO handling

This is to align with newer platforms.

Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50963
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/fizz/variants/fizz/overridetree.cb

@@ -1,7 +1,7 @@
 chip soc/intel/skylake
 
 	# Use default SD card detect GPIO configuration
-	register "sdcard_cd_gpio_default" = "GPP_A7"
+	register "sdcard_cd_gpio" = "GPP_A7"
 
 	device domain 0 on
 		device pci 14.0 on

src/mainboard/google/glados/variants/cave/overridetree.cb

@@ -23,7 +23,7 @@ chip soc/intel/skylake
 	register "tcc_offset" = "10"
 
 	# Use default SD card detect GPIO configuration
-	register "sdcard_cd_gpio_default" = "GPP_A7"
+	register "sdcard_cd_gpio" = "GPP_A7"
 
 	device domain 0 on
 		device pci 15.0 on

src/mainboard/google/glados/variants/sentry/overridetree.cb

@@ -16,7 +16,7 @@ chip soc/intel/skylake
 	register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
 
 	# Use default SD card detect GPIO configuration
-	register "sdcard_cd_gpio_default" = "GPP_A7"
+	register "sdcard_cd_gpio" = "GPP_A7"
 
 	device domain 0 on
 		device pci 15.0 on

src/mainboard/google/poppy/variants/baseboard/devicetree.cb

@@ -251,7 +251,7 @@ chip soc/intel/skylake
 	register "tcc_offset" = "10"     # TCC of 90C
 
 	# Use default SD card detect GPIO configuration
-	register "sdcard_cd_gpio_default" = "GPP_E15"
+	register "sdcard_cd_gpio" = "GPP_E15"
 
 	device cpu_cluster 0 on
 		device lapic 0 on end

src/mainboard/google/poppy/variants/nautilus/devicetree.cb

@@ -273,7 +273,7 @@ chip soc/intel/skylake
 	register "tcc_offset" = "10"     # TCC of 90C
 
 	# Use default SD card detect GPIO configuration
-	register "sdcard_cd_gpio_default" = "GPP_E15"
+	register "sdcard_cd_gpio" = "GPP_E15"
 
 	device cpu_cluster 0 on
 		device lapic 0 on end

src/mainboard/google/poppy/variants/rammus/devicetree.cb

@@ -232,7 +232,7 @@ chip soc/intel/skylake
 	register "tcc_offset" = "10"     # TCC of 90C
 
 	# Use default SD card detect GPIO configuration
-	register "sdcard_cd_gpio_default" = "GPP_E15"
+	register "sdcard_cd_gpio" = "GPP_E15"
 
 	device cpu_cluster 0 on
 		device lapic 0 on end

src/mainboard/google/poppy/variants/soraka/devicetree.cb

@@ -252,7 +252,7 @@ chip soc/intel/skylake
 	register "tcc_offset" = "10"     # TCC of 90C
 
 	# Use default SD card detect GPIO configuration
-	register "sdcard_cd_gpio_default" = "GPP_E15"
+	register "sdcard_cd_gpio" = "GPP_E15"
 
 	device cpu_cluster 0 on
 		device lapic 0 on end

src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb

@@ -150,7 +150,7 @@ chip soc/intel/skylake
 
 
 	# Use default SD card detect GPIO configuration
-	register "sdcard_cd_gpio_default" = "GPP_G5"
+	register "sdcard_cd_gpio" = "GPP_G5"
 
 	# Lock Down
 	register "common_soc_config" = "{

src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb

@@ -156,7 +156,7 @@ chip soc/intel/skylake
 	}"
 
 	# Use default SD card detect GPIO configuration
-	#register "sdcard_cd_gpio_default" = "GPP_D10"
+	#register "sdcard_cd_gpio" = "GPP_D10"
 
 	device domain 0 on
 		device pci 17.0 on  end # SATA

src/mainboard/intel/kunimitsu/devicetree.cb

@@ -156,7 +156,7 @@ chip soc/intel/skylake
 	register "SendVrMbxCmd" = "2"
 
 	# Use default SD card detect GPIO configuration
-	register "sdcard_cd_gpio_default" = "GPP_A7"
+	register "sdcard_cd_gpio" = "GPP_A7"
 
 	# Lock Down
 	register "common_soc_config" = "{

src/mainboard/intel/saddlebrook/devicetree.cb

@@ -197,7 +197,7 @@ chip soc/intel/skylake
 	register "SendVrMbxCmd" = "2"
 
 	# Use default SD card detect GPIO configuration
-	#register "sdcard_cd_gpio_default" = "GPP_A7"
+	#register "sdcard_cd_gpio" = "GPP_A7"
 
 	device cpu_cluster 0 on
 		device lapic 0 on end

src/soc/intel/skylake/chip.h

@@ -427,12 +427,9 @@ struct soc_intel_skylake_config {
 	 *
 	 * GpioInt (Edge, ActiveBoth, SharedAndWake, PullNone, 10000,
 	 *          "\\_SB.PCI0.GPIO", 0, ResourceConsumer)
-	 *          { sdcard_cd_gpio_default }
+	 *          { sdcard_cd_gpio }
 	 */
-	unsigned int sdcard_cd_gpio_default;
-
-	/* Use custom SD card detect GPIO configuration */
-	struct acpi_gpio sdcard_cd_gpio;
+	unsigned int sdcard_cd_gpio;
 
 	/* Wake Enable Bitmap for USB2 ports */
 	u16 usb2_wake_enable_bitmap;

src/soc/intel/skylake/sd.c

@@ -3,26 +3,22 @@
 #include <intelblocks/sd.h>
 #include "chip.h"
 
-int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, const struct device *dev)
+int sd_fill_soc_gpio_info(struct acpi_gpio *gpio, const struct device *dev)
 {
 	config_t *config = config_of(dev);
 
-	/* Nothing to write if GPIO is not set in devicetree */
-	if (!config->sdcard_cd_gpio_default && !config->sdcard_cd_gpio.pins[0])
+	if (!config->sdcard_cd_gpio)
 		return -1;
 
-	if (config->sdcard_cd_gpio_default) {
-		gpio->type = ACPI_GPIO_TYPE_INTERRUPT;
-		gpio->pull = ACPI_GPIO_PULL_NONE;
-		gpio->irq.mode = ACPI_IRQ_EDGE_TRIGGERED;
-		gpio->irq.polarity = ACPI_IRQ_ACTIVE_BOTH;
-		gpio->irq.shared = ACPI_IRQ_SHARED;
-		gpio->irq.wake = ACPI_IRQ_WAKE;
-		gpio->interrupt_debounce_timeout = 10000; /* 100ms */
-		gpio->pin_count = 1;
-		gpio->pins[0] = config->sdcard_cd_gpio_default;
-	} else
-		*gpio = config->sdcard_cd_gpio;
+	gpio->type = ACPI_GPIO_TYPE_INTERRUPT;
+	gpio->pull = ACPI_GPIO_PULL_NONE;
+	gpio->irq.mode = ACPI_IRQ_EDGE_TRIGGERED;
+	gpio->irq.polarity = ACPI_IRQ_ACTIVE_BOTH;
+	gpio->irq.shared = ACPI_IRQ_SHARED;
+	gpio->irq.wake = ACPI_IRQ_WAKE;
+	gpio->interrupt_debounce_timeout = 10000; /* 100ms */
+	gpio->pin_count = 1;
+	gpio->pins[0] = config->sdcard_cd_gpio;
 
 	return 0;
 }