diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
index e1ee71a5a7..bbcfa28e06 100644
--- a/src/cpu/amd/model_10xxx/fidvid.c
+++ b/src/cpu/amd/model_10xxx/fidvid.c
@@ -738,7 +738,7 @@ static u32 init_fidvid_core(u32 nodeid, u32 coreid)
 
 }
 
-static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid)
+static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid)
 {
 	u32 send;
 
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index c21a13551c..a256f9c508 100644
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -157,7 +157,7 @@ static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue)
 }
 
 #if CONFIG_SET_FIDVID
-static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid);
+static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid);
 #endif
 
 static inline __attribute__ ((always_inline))
@@ -346,8 +346,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
 				printk(BIOS_DEBUG,
 				       "init_fidvid_ap(stage1) apicid: %02x\n",
 				       apicid);
-				init_fidvid_ap(bsp_apicid, apicid, id.nodeid,
-					       id.coreid);
+				init_fidvid_ap(apicid, id.nodeid, id.coreid);
 			}
 		}
 #endif
diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h
index 6f03be886d..566e1fbbb0 100644
--- a/src/northbridge/amd/amdht/AsPsDefs.h
+++ b/src/northbridge/amd/amdht/AsPsDefs.h
@@ -58,7 +58,6 @@
 #define PS_NB_VID_SHFT 25		/* P-state bit shift for NbVid */
 #define PS_BOTH_VID_OFF 0x01ff01ff	/* Mask NbVid & CpuVid */
 #define PS_CPU_NB_VID_SHFT 16		/* P-state bit shift from CpuVid to NbVid */
-#define PS_NB_VID_SHFT 25		/* P-state NBVID shift */
 #define PS_DIS 0x7fffffff		/* disable P-state reg */
 #define PS_EN 0x80000000		/* enable P-state reg */
 #define PS_CPU_FID_MASK 0x03f           /* MSRC001_00[68:64][CpuFid]