soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill

The dimm_info structure (defined in src/include/memory_info.h)
currently does not hold information about the DIMM's
node/controller ID.

This patch extends the dimm_info structure by adding a new field for
the node ID, called node_num. Also, adapt the dimm_info_fill()
function accordingly to populate the newly-added field.

Background: These changes are necessary for the Atlas mainboard, where
we are currently experiencing issues with the DIMMs device/bank
locator. Our 2 DIMMs share the same CHANNEL and DIMM ID but have a
distinct NODE ID. By looking at the smbios table we see
Channel-0-DIMM-0 for both DIMMs. Thus, we need their NODE IDs in order
to distinguish them.

This patch was tested by building and booting for the Alderlake-P
RVP board, which has the same DIMM slot configuration as the
Prodrive Atlas mainboard.

Signed-off-by: David Milosevic <David.Milosevic@9elements.com>
Change-Id: I6ffa5bdff0ba0e3c4a4a51f2419291fd1278cd68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68525
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/include/memory_info.h

@@ -33,7 +33,17 @@ struct dimm_info {
 	 */
 	uint16_t ddr_frequency;
 	uint8_t rank_per_dimm;
+	/*
+	 * Memory-Controller-ID
+	 */
+	uint8_t ctrlr_num;
+	/*
+	 * Channel-ID
+	 */
 	uint8_t channel_num;
+	/*
+	 * DIMM-ID
+	 */
 	uint8_t dimm_num;
 	uint8_t bank_locator;
 	/*

src/soc/intel/alderlake/romstage/romstage.c

@@ -114,7 +114,8 @@ static void save_dimm_info(void)
 					meminfo_hob->VddVoltage[memProfNum],
 					meminfo_hob->EccSupport,
 					src_dimm->MfgId,
-					src_dimm->SpdModuleType);
+					src_dimm->SpdModuleType,
+					node);
 				index++;
 			}
 		}

src/soc/intel/apollolake/meminit_util_apl.c

@@ -82,6 +82,7 @@ void save_lpddr4_dimm_info_part_num(const char *dram_part_num)
 				0,
 				0,
 				src_dimm->MfgId,
+				0,
 				0);
 			index++;
 		}

src/soc/intel/apollolake/meminit_util_glk.c

@@ -88,7 +88,8 @@ void save_lpddr4_dimm_info_part_num(const char *dram_part_num)
 				    0,
 				    0,
 				    src_dimm->MfgId,
-				    src_dimm->SpdModuleType);
+				    src_dimm->SpdModuleType,
+				    node);
 				index++;
 			}
 		}

src/soc/intel/cannonlake/romstage/romstage.c

@@ -107,7 +107,8 @@ static void save_dimm_info(void)
 				memory_info_hob->VddVoltage[memProfNum],
 				memory_info_hob->EccSupport,
 				src_dimm->MfgId,
-				src_dimm->SpdModuleType);
+				src_dimm->SpdModuleType,
+				0);
 			index++;
 		}
 	}

src/soc/intel/common/smbios.c

@@ -14,7 +14,7 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type,
 		u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id,
 		const char *module_part_num, size_t module_part_number_size,
 		const u8 *module_serial_num, u16 data_width, u32 vdd_voltage,
-		bool ecc_support, u16 mod_id, u8 mod_type)
+		bool ecc_support, u16 mod_id, u8 mod_type, u8 ctrlr_id)
 {
 	dimm->mod_id = mod_id;
 	dimm->mod_type = mod_type;
@@ -24,6 +24,8 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type,
 	dimm->rank_per_dimm = rank_per_dimm;
 	dimm->channel_num = channel_id;
 	dimm->dimm_num = dimm_id;
+	dimm->ctrlr_num = ctrlr_id;
+
 	if (vdd_voltage > 0xFFFF) {
 		dimm->vdd_voltage = 0xFFFF;
 	} else {

src/soc/intel/common/smbios.h

@@ -14,6 +14,6 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type,
 		u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id,
 		const char *module_part_num, size_t module_part_number_size,
 		const u8 *module_serial_num, u16 data_width, u32 vdd_voltage,
-		bool ecc_support, u16 mod_id, u8 mod_type);
+		bool ecc_support, u16 mod_id, u8 mod_type, u8 ctrlr_id);
 
 #endif /* _COMMON_SMBIOS_H_ */

src/soc/intel/elkhartlake/romstage/romstage.c

@@ -112,7 +112,8 @@ static void save_dimm_info(void)
 					meminfo_hob->VddVoltage[memProfNum],
 					meminfo_hob->EccSupport,
 					src_dimm->MfgId,
-					src_dimm->SpdModuleType);
+					src_dimm->SpdModuleType,
+					node);
 				index++;
 			}
 		}

src/soc/intel/icelake/romstage/romstage.c

@@ -96,7 +96,8 @@ static void save_dimm_info(void)
 				memory_info_hob->VddVoltage[memProfNum],
 				memory_info_hob->EccSupport,
 				src_dimm->MfgId,
-				src_dimm->SpdModuleType);
+				src_dimm->SpdModuleType,
+				0);
 			index++;
 		}
 	}

src/soc/intel/jasperlake/romstage/romstage.c

@@ -112,7 +112,8 @@ static void save_dimm_info(void)
 					meminfo_hob->VddVoltage[memProfNum],
 					meminfo_hob->EccSupport,
 					src_dimm->MfgId,
-					src_dimm->SpdModuleType);
+					src_dimm->SpdModuleType,
+					node);
 				index++;
 			}
 		}

src/soc/intel/meteorlake/romstage/romstage.c

@@ -106,7 +106,8 @@ static void save_dimm_info(void)
 						meminfo_hob->VddVoltage[memProfNum],
 						meminfo_hob->EccSupport,
 					src_dimm->MfgId,
-					src_dimm->SpdModuleType);
+					src_dimm->SpdModuleType,
+					node);
 				index++;
 			}
 		}

src/soc/intel/skylake/romstage/romstage.c

@@ -111,7 +111,8 @@ static void save_dimm_info(void)
 				memory_info_hob->VddVoltage[memProfNum],
 				memory_info_hob->EccSupport,
 				src_dimm->MfgId,
-				src_dimm->SpdModuleType);
+				src_dimm->SpdModuleType,
+				0);
 			index++;
 		}
 	}

src/soc/intel/tigerlake/romstage/romstage.c

@@ -112,7 +112,8 @@ static void save_dimm_info(void)
 					meminfo_hob->VddVoltage[memProfNum],
 					meminfo_hob->EccSupport,
 					src_dimm->MfgId,
-					src_dimm->SpdModuleType);
+					src_dimm->SpdModuleType,
+					node);
 				index++;
 			}
 		}

src/soc/intel/xeon_sp/cpx/romstage.c

@@ -131,7 +131,8 @@ void save_dimm_info(void)
 					vdd_voltage,
 					true, /* hard-coded as ECC supported */
 					src_dimm.VendorID,
-					src_dimm.actKeyByte2);
+					src_dimm.actKeyByte2,
+					0);
 				index++;
 			}
 		}