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mb/siemens/{mc_apl2,...,mc_apl6}: Do early UART pad configuration 

With commit 405f229689 (soc/intel/*: drop UART pad configuration from
common code) the UART pad configuration was dropped from common SoC
code. Through a second commit 5ff17ed393 (mb/siemens/mc_apl1: do UART
pad configuration at board-level) the UART pad configuration was made
for mc_apl1 baseboard. This change is also needed for all other mc_apl
boards.

Change-Id: If78726d9b141e4e7580cca3267f49c1a5b95d7fa
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Mario Scheithauer 2021-05-25 13:42:28 +02:00 committed by Patrick Georgi
parent 0a88c6057a
commit 6be8a5138a
5 changed files with 16 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c
View File

@ -528,6 +528,9 @@ const struct pad_config *variant_gpio_table(size_t *num)
/* GPIOs needed prior to ramstage. */
static const struct pad_config early_gpio_table[] = {
/* UART */
PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */
PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */
/* Not connected */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_0, DN_20K, PWROK, NF1, HIZCRx0, SAME),

3
src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c
View File

@ -357,6 +357,9 @@ const struct pad_config *variant_gpio_table(size_t *num)
/* GPIOs needed prior to ramstage. */
static const struct pad_config early_gpio_table[] = {
/* UART */
PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */
PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */
/* Debug tracing. */
PAD_CFG_GPI(GPIO_0, DN_20K, DEEP), /* TRACE_0_CLK_VNN */

4
src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c
View File

@ -337,6 +337,10 @@ const struct pad_config *variant_gpio_table(size_t *num)
/* GPIOs needed prior to ramstage. */
static const struct pad_config early_gpio_table[] = {
/* UART */
PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */
PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */
/* Southwest Community */
/* Multiplexed I2C7 */

3
src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c
View File

@ -357,6 +357,9 @@ const struct pad_config *variant_gpio_table(size_t *num)
/* GPIOs needed prior to ramstage. */
static const struct pad_config early_gpio_table[] = {
/* UART */
PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */
PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */
/* Debug tracing. */
PAD_CFG_GPI(GPIO_0, DN_20K, DEEP), /* TRACE_0_CLK_VNN */

3
src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c
View File

@ -357,6 +357,9 @@ const struct pad_config *variant_gpio_table(size_t *num)
/* GPIOs needed prior to ramstage. */
static const struct pad_config early_gpio_table[] = {
/* UART */
PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */
PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */
/* Debug tracing. */
PAD_CFG_GPI(GPIO_0, DN_20K, DEEP), /* TRACE_0_CLK_VNN */