sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetree

Set up generic decode ranges based on the devicetree settings.

Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Arthur Heymans 2019-06-16 23:29:23 +02:00 committed by Patrick Georgi
parent 4821a0e135
commit 6beaef983a
42 changed files with 38 additions and 128 deletions

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@ -23,10 +23,6 @@
void pch_enable_lpc(void)
{
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000);
}

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@ -33,12 +33,6 @@ void pch_enable_lpc(void)
u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN;
pci_write_config16(dev, LPC_EN, lpc_config);
/* Map 1 byte to the LPC bus. */
pci_write_config32(dev, LPC_GEN1_DEC, 0x00164d);
/* Map a range for the runtime_port registers to the LPC bus. */
pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181);
#if CONFIG(DRIVERS_UART_8250IO)
/* Enable COM1 */
if (sio1007_enable_uart_at(SIO_PORT)) {

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@ -30,7 +30,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);

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@ -33,13 +33,6 @@ void pch_enable_lpc(void)
/* EC Decode Range Port60/64 and Port62/66 */
/* Enable EC and PS/2 Keyboard/Mouse*/
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN);
/* EC Decode Range Port68/6C */
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x40001);
/* EC Decode Range Port 380-387 */
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x380 | 0x40001);
}
void mainboard_rcba_config(void)

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@ -34,28 +34,12 @@
void pch_enable_lpc(void)
{
const struct device *lpc;
const struct southbridge_intel_bd82x6x_config *config = NULL;
lpc = pcidev_on_root(0x1f, 0);
if (!lpc)
return;
if (lpc->chip_info)
config = lpc->chip_info;
if (!config)
return;
/* Set COM1/COM2 decode range */
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | \
GAMEL_LPC_EN | COMA_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec);
pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec);
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
}
void mainboard_rcba_config(void)

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@ -31,12 +31,6 @@ void pch_enable_lpc(void)
/* Parrot EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN);
/* Map EC_IO decode to the LPC bus */
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (EC_IO & ~3) | 0x00040001);
/* Map EC registers 68/6C decode to the LPC bus */
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, (68 & ~3) | 0x00040001);
}
void mainboard_rcba_config(void)

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@ -41,9 +41,6 @@ void pch_enable_lpc(void)
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
CNF1_LPC_EN | FDD_LPC_EN);
/* Stout EC Decode Range Port68/6C */
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 | 0x40001));
}
void mainboard_rcba_config(void)

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@ -46,6 +46,7 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
# mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"

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@ -28,8 +28,6 @@ void pch_enable_lpc(void)
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
/* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)

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@ -55,6 +55,7 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
# mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"

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@ -27,8 +27,6 @@ void pch_enable_lpc(void)
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
/* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)

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@ -54,6 +54,7 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
# mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"

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@ -34,8 +34,6 @@ void pch_enable_lpc(void)
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
LPT_LPC_EN | COMA_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
/* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)

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@ -55,6 +55,7 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
# mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"

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@ -33,8 +33,6 @@ void pch_enable_lpc(void)
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
LPT_LPC_EN | COMA_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
/* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)

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@ -43,6 +43,7 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
# mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"

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@ -34,8 +34,6 @@ void pch_enable_lpc(void)
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
LPT_LPC_EN | COMA_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
/* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)

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@ -46,6 +46,7 @@ chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
# mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"

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@ -30,8 +30,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
/* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)

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@ -46,6 +46,7 @@ chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
# mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"

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@ -33,8 +33,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
/* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)

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@ -44,8 +44,11 @@ chip northbridge/intel/sandybridge
register "sata_port_map" = "0x3f"
register "gen1_dec" = "0x00fc1601"
# runtime_port registers
register "gen2_dec" = "0x000c0181"
# SuperIO range is 0x700-0x73f
register "gen2_dec" = "0x003c0701"
register "gen3_dec" = "0x003c0701"
register "c2_latency" = "1"
register "p_cnt_throttling_supported" = "0"

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@ -39,12 +39,6 @@ void pch_enable_lpc(void)
u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN;
pci_write_config16(dev, LPC_EN, lpc_config);
/* Map 256 bytes at 0x1600 to the LPC bus. */
pci_write_config32(dev, LPC_GEN1_DEC, 0xfc1601);
/* Map a range for the runtime_port registers to the LPC bus. */
pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181);
/* Enable COM1 */
if (sio1007_enable_uart_at(SIO_PORT)) {
pci_write_config16(dev, LPC_EN,

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@ -29,10 +29,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
LPT_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1611);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x040069);
pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x0c0701);
}
void mainboard_rcba_config(void)

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@ -30,9 +30,6 @@
void pch_enable_lpc(void)
{
pci_write_config16(PCH_LPC_DEV, LPC_EN, MC_LPC_EN | KBC_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc0701);
pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0xc0069);
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0xc06a1);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
/* Memory map KB9012 EC registers */

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@ -56,10 +56,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}

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@ -56,10 +56,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}

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@ -55,9 +55,6 @@ void pch_enable_lpc(void)
/* Enable TPM, EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC,
(0x0c << 16) | EC_LENOVO_PMH7_BASE | 1);
}
void mainboard_rcba_config(void)

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@ -26,10 +26,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}

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@ -58,10 +58,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}

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@ -58,10 +58,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}

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@ -26,11 +26,6 @@ void pch_enable_lpc(void)
/* Enable TPM, EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c1611);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x00040069);
pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x000c0701);
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x000c06a1);
}
void mainboard_rcba_config(void)

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@ -35,10 +35,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}

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@ -34,10 +34,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}

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@ -31,10 +31,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}

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@ -61,6 +61,7 @@ chip northbridge/intel/sandybridge
# EC range is 0xa00-0xa3f
register "gen1_dec" = "0x003c0a01"
register "gen2_dec" = "0x003c0b01"
register "gen3_dec" = "0x00fc1601"
register "c2_latency" = "1"
register "p_cnt_throttling_supported" = "0"

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@ -43,9 +43,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN |
KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
/* map full 256 bytes at 0x1600 to the LPC bus */
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601);
try_enabling_LPC47N207_uart();
#else
/* Enable SuperIO + EC + KBC */

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@ -50,6 +50,7 @@ chip northbridge/intel/sandybridge
register "c2_latency" = "1"
register "p_cnt_throttling_supported" = "0"
register "gen1_dec" = "0x00fc1601"
# SuperIO range is 0x700-0x73f
register "gen2_dec" = "0x003c0701"

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@ -55,9 +55,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\
CNF2_LPC_EN | COMA_LPC_EN);
/* map full 256 bytes at 0x1600 to the LPC bus */
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601);
try_enabling_LPC47N207_uart();
#else
/* Enable SuperIO + PS/2 Keyboard/Mouse */

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@ -24,10 +24,6 @@
void pch_enable_lpc(void)
{
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0291);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0a01);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);
}

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@ -27,6 +27,7 @@
#include <northbridge/intel/sandybridge/sandybridge.h>
#include "pch.h"
#include "chip.h"
#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
@ -258,10 +259,31 @@ static void pch_generic_setup(void)
write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */
}
static void pch_enable_lpc_gen_decode(void)
{
const struct device *dev = pcidev_on_root(0x1f, 0);
const struct southbridge_intel_bd82x6x_config *config = NULL;
/* Set up generic decode ranges */
if (!dev)
return;
if (dev->chip_info)
config = dev->chip_info;
if (!config)
return;
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec);
pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec);
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
}
void early_pch_init(void)
{
pch_enable_lpc();
pch_enable_lpc_gen_decode();
pch_enable_bars();
pch_generic_setup();

View File

@ -28,7 +28,7 @@ func (b bd82x6x) writeGPIOSet(ctx Context, sb *os.File,
}
for i := uint(0); i < max; i++ {
if ((constraint>>i)&1 == 1) {
if (constraint>>i)&1 == 1 {
fmt.Fprintf(sb, " .gpio%d = %s,\n",
(set-1)*32+i,
bits[partno][(val>>i)&1])
@ -236,8 +236,8 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
"p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)),
"c2_latency": FormatHexLE16(FADT[96:98]),
"docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)),
"spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]),
"spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4] &^ (1 << 23)),
"spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]),
"spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4]&^(1<<23)),
},
PCISlots: []PCISlot{
PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"},
@ -315,10 +315,6 @@ void pch_enable_lpc(void)
{
`)
RestorePCI16Simple(sb, addr, 0x82)
RestorePCI32Simple(sb, addr, 0x84)
RestorePCI32Simple(sb, addr, 0x88)
RestorePCI32Simple(sb, addr, 0x8c)
RestorePCI32Simple(sb, addr, 0x90)
RestorePCI16Simple(sb, addr, 0x80)