soc/qualcomm/qcs405: Add MMU support
Initialize 1st 4GB as Device Memory, except: * 1st page: NULL address * System_IMEM: Cached SRAM * Boot_IMEM: Cached SRAM Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -5,6 +5,7 @@ ifeq ($(CONFIG_SOC_QUALCOMM_QCS405),y)
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bootblock-y += bootblock.c
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bootblock-y += timer.c
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bootblock-y += spi.c
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bootblock-y += mmu.c
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################################################################################
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verstage-y += timer.c
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@ -14,8 +14,9 @@
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*/
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#include <bootblock_common.h>
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#include <soc/mmu.h>
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void bootblock_soc_init(void)
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{
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qcs405_mmu_init();
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}
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_QUALCOMM_QCS405_MMU_H__
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#define _SOC_QUALCOMM_QCS405_MMU_H__
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void qcs405_mmu_init(void);
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#endif // _SOC_QUALCOMM_QCS405_MMU_H_
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@ -0,0 +1,25 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_QUALCOMM_QCS405_SYMBOLS_H_
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#define _SOC_QUALCOMM_QCS405_SYMBOLS_H_
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#include <symbols.h>
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#include <types.h>
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DECLARE_REGION(ssram);
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DECLARE_REGION(bsram);
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#endif // _SOC_QUALCOMM_QCS405_SYMBOLS_H_
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@ -0,0 +1,32 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <symbols.h>
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#include <arch/mmu.h>
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#include <arch/cache.h>
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#include <soc/mmu.h>
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#include <soc/symbols.h>
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void qcs405_mmu_init(void)
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{
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mmu_init();
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mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)),
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MA_DEV | MA_S | MA_RW);
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mmu_config_range((void *)_ssram, REGION_SIZE(ssram), MA_MEM | MA_S | MA_RW);
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mmu_config_range((void *)_bsram, REGION_SIZE(bsram), MA_MEM | MA_S | MA_RW);
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mmu_enable();
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}
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