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soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT 

Select NO_S0IX_SUPPORT for `starlabs/starbook` and `atlas/prodrive`
so their configurations are unchanged.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I718952165daa6471f11e8025e745fe7c249d3b46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72800
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2023-02-06 09:23:47 +00:00 committed by Lean Sheng Tan
parent dbb97c3243
commit 6bfca1b689
5 changed files with 5 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/prodrive/atlas/Kconfig
View File

@ -9,9 +9,9 @@ config BOARD_PRODRIVE_ATLAS_BASEBOARD
select MAINBOARD_HAS_TPM2
select MAINBOARD_USES_IFD_EC_REGION
select MEMORY_MAPPED_TPM
select NO_S0IX_SUPPORT
select PCIEXP_SUPPORT_RESIZABLE_BARS
select SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_ALDERLAKE_S3
if BOARD_PRODRIVE_ATLAS_BASEBOARD

3
src/mainboard/starlabs/starbook/Kconfig
View File

@ -10,6 +10,7 @@ config BOARD_STARLABS_STARBOOK_SERIES
select INTEL_GMA_HAVE_VBT
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_TPM2
select NO_S0IX_SUPPORT
select NO_UART_ON_SUPERIO
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SYSTEM_TYPE_LAPTOP
@ -50,7 +51,6 @@ config BOARD_STARLABS_STARBOOK_TGL
select SOC_INTEL_COMMON_BLOCK_TCSS
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
select SOC_INTEL_TIGERLAKE
select SOC_INTEL_TIGERLAKE_S3
select SPI_FLASH_WINBOND
select TPM_MEASURED_BOOT
@ -65,7 +65,6 @@ config BOARD_STARLABS_STARBOOK_ADL
select MEMORY_MAPPED_TPM
select SOC_INTEL_ALDERLAKE
select SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_ALDERLAKE_S3
select SPI_FLASH_WINBOND
select TPM_MEASURED_BOOT
select PCIEXP_SUPPORT_RESIZABLE_BARS

1
src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
View File

@ -19,7 +19,6 @@ chip soc/intel/tigerlake
register "CnviBtAudioOffload" = "1"
register "enable_c6dram" = "1"
register "SaGv" = "SaGv_Enabled"
register "TcssD3ColdDisable" = "1"
# FSP Silicon
# Serial I/O

2
src/soc/intel/alderlake/fsp_params.c
View File

@ -648,7 +648,7 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
/* D3Hot and D3Cold for TCSS */
s_cfg->D3HotEnable = !config->tcss_d3_hot_disable;
s_cfg->D3ColdEnable = !CONFIG(SOC_INTEL_ALDERLAKE_S3) && !config->tcss_d3_cold_disable;
s_cfg->D3ColdEnable = CONFIG(D3COLD_SUPPORT) && !config->tcss_d3_cold_disable;
s_cfg->UsbTcPortEn = 0;
for (int i = 0; i < MAX_TYPE_C_PORTS; i++) {

3
src/soc/intel/tigerlake/fsp_params.c
View File

@ -323,11 +323,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* D3Hot and D3Cold for TCSS */
params->D3HotEnable = !config->TcssD3HotDisable;
cpu_id = cpu_get_cpuid();
if (cpu_id == CPUID_TIGERLAKE_A0)
params->D3ColdEnable = 0;
else
params->D3ColdEnable = !config->TcssD3ColdDisable;
params->D3ColdEnable = CONFIG(D3COLD_SUPPORT);
params->UsbTcPortEn = config->UsbTcPortEn;
params->TcssAuxOri = config->TcssAuxOri;