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mb/google/var/primus4es: Add gpios to lock 

Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.

BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
primus boots successfully to kernel.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I71f7391df6d827b75f87e54e17f6f7983a9e829b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Eric Lai 2022-02-08 11:11:50 +08:00 committed by Felix Held
parent 0bcf771cd2
commit 6c10007b42
1 changed files with 6 additions and 6 deletions
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12
src/mainboard/google/brya/variants/primus4es/gpio.c
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@ -23,13 +23,13 @@ static const struct pad_config override_gpio_table[] = {
/* B2 : VRALERT# ==> NC */ /* B2 : VRALERT# ==> NC */
PAD_NC(GPP_B2, NONE), PAD_NC(GPP_B2, NONE),
/* B3 : PROC_GP2 ==> eMMC_PERST_L */ /* B3 : PROC_GP2 ==> eMMC_PERST_L */
PAD_CFG_GPO(GPP_B3, 1, DEEP), PAD_CFG_GPO_LOCK(GPP_B3, 1, LOCK_CONFIG),
/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
/* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
/* B15 : TIME_SYNC0 ==> NC */ /* B15 : TIME_SYNC0 ==> NC */
PAD_NC(GPP_B15, NONE), PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
/* C3 : SML0CLK ==> NC */ /* C3 : SML0CLK ==> NC */
PAD_NC(GPP_C3, NONE), PAD_NC(GPP_C3, NONE),
@ -37,17 +37,17 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_C4, NONE), PAD_NC(GPP_C4, NONE),
/* D3 : ISH_GP3 ==> NC */ /* D3 : ISH_GP3 ==> NC */
PAD_NC(GPP_D3, NONE), PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
/* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
/* D6 : SRCCLKREQ1# ==> NC */ /* D6 : SRCCLKREQ1# ==> NC */
PAD_NC(GPP_D6, NONE), PAD_NC(GPP_D6, NONE),
/* D13 : ISH_UART0_RXD ==> NC */ /* D13 : ISH_UART0_RXD ==> NC */
PAD_NC(GPP_D13, NONE), PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
/* D14 : ISH_UART0_TXD ==> USB_A1_RT_RST_ODL */ /* D14 : ISH_UART0_TXD ==> USB_A1_RT_RST_ODL */
PAD_CFG_GPO(GPP_D14, 1, DEEP), PAD_CFG_GPO_LOCK(GPP_D14, 1, LOCK_CONFIG),
/* D18 : UART1_TXD ==> SD_PE_RST_L */ /* D18 : UART1_TXD ==> SD_PE_RST_L */
PAD_CFG_GPO(GPP_D18, 1, PLTRST), PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG),
/* E3 : PROC_GP0 ==> NC */ /* E3 : PROC_GP0 ==> NC */
PAD_NC(GPP_E3, NONE), PAD_NC(GPP_E3, NONE),