drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config

Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate
older x86 platforms that don't allow writing to SPI flash when early
stages are running XIP from flash.  If
BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected,
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y.  This allows for current platforms
that write to flash in the earlier stages, assuming that they have
that capability.

BUG=b:150502246
BRANCH=None

TEST=diff the coreboot.rom files resulting from running
     ./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless
     with and without this change to make sure that there was no
     difference.  Also did this for GOOGLE_CANDY board, which is
     baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
     enabled).

Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

src/cpu/intel/haswell/Kconfig

@@ -7,6 +7,7 @@ if CPU_INTEL_HASWELL
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ARCH_ALL_STAGES_X86_32
+	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select MMX
 	select SSE2
 	select UDELAY_TSC

src/cpu/intel/model_2065x/Kconfig

@@ -6,6 +6,7 @@ if CPU_INTEL_MODEL_2065X
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ARCH_ALL_STAGES_X86_32
+	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select SSE2
 	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER

src/cpu/intel/model_206ax/Kconfig

@@ -6,6 +6,7 @@ if CPU_INTEL_MODEL_206AX
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ARCH_ALL_STAGES_X86_32
+	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select MMX
 	select SSE2
 	select UDELAY_TSC

src/drivers/spi/Kconfig

@@ -42,8 +42,20 @@ config BOOT_DEVICE_SPI_FLASH_RW_NOMMAP
 	  Provide common implementation of the RW boot device that
 	  doesn't provide mmap() operations.
 
+config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
+	bool
+	default n
+	depends on BOOT_DEVICE_SPI_FLASH_RW_NOMMAP
+	help
+	  For platforms who do not allow writes to SPI flash in early
+	  stages like romstage.  Not selecting this config will result
+	  in the auto-selection of
+	  BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if
+	  BOOT_DEVICE_SPI_FLASH_RW_NOMMAP is selected by the platform.
+
 config BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY
 	bool
+	default y if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP && !BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	default n
 	depends on BOOT_DEVICE_SPI_FLASH_RW_NOMMAP
 	help

src/northbridge/intel/x4x/Kconfig

@@ -12,6 +12,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select INTEL_GMA_ACPI
 	select CACHE_MRC_SETTINGS
 	select PARALLEL_MP
+	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 
 config CBFS_SIZE
 	hex

src/soc/amd/picasso/Kconfig

@@ -44,7 +44,6 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_PSP_GEN2
 	select PROVIDES_ROM_SHARING
 	select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
-	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
 	select PARALLEL_MP
 	select PARALLEL_MP_AP_WORK
 	select HAVE_SMI_HANDLER

src/soc/amd/stoneyridge/Kconfig

@@ -38,7 +38,6 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_S3
 	select SOC_AMD_COMMON_BLOCK_SMBUS
 	select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
-	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
 	select PARALLEL_MP
 	select PARALLEL_MP_AP_WORK
 	select HAVE_SMI_HANDLER

src/soc/intel/alderlake/Kconfig

@@ -11,7 +11,6 @@ config CPU_SPECIFIC_OPTIONS
 	select ARCH_BOOTBLOCK_X86_32
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_VERSTAGE_X86_32
-	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS
 	select CPU_INTEL_COMMON

src/soc/intel/apollolake/Kconfig

@@ -22,7 +22,6 @@ config CPU_SPECIFIC_OPTIONS
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select ACPI_NO_PCAT_8259
 	select ARCH_ALL_STAGES_X86_32
-	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	# CPU specific options
 	select CPU_INTEL_COMMON

src/soc/intel/baytrail/Kconfig

@@ -9,6 +9,7 @@ config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select ARCH_ALL_STAGES_X86_32
+	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS
 	select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED

src/soc/intel/braswell/Kconfig

@@ -9,6 +9,7 @@ config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select ARCH_ALL_STAGES_X86_32
+	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS
 	select SUPPORT_CPU_UCODE_IN_CBFS

src/soc/intel/broadwell/Kconfig

@@ -9,6 +9,7 @@ config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select ARCH_ALL_STAGES_X86_32
+	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS
 	select MRC_SETTINGS_PROTECT

src/soc/intel/cannonlake/Kconfig

@@ -75,7 +75,6 @@ config CPU_SPECIFIC_OPTIONS
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select ACPI_NHLT
 	select ARCH_ALL_STAGES_X86_32
-	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS
 	select CPU_INTEL_COMMON

src/soc/intel/denverton_ns/Kconfig

@@ -10,7 +10,6 @@ if SOC_INTEL_DENVERTON_NS
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ARCH_ALL_STAGES_X86_32
-	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select DEBUG_GPIO
 	select SOC_INTEL_COMMON

src/soc/intel/elkhartlake/Kconfig

@@ -9,7 +9,6 @@ config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select ARCH_ALL_STAGES_X86_32
-	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS
 	select CPU_INTEL_COMMON

src/soc/intel/icelake/Kconfig

@@ -9,7 +9,6 @@ config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select ARCH_ALL_STAGES_X86_32
-	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE

src/soc/intel/jasperlake/Kconfig

@@ -9,7 +9,6 @@ config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select ARCH_ALL_STAGES_X86_32
-	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS
 	select CPU_INTEL_COMMON

src/soc/intel/skylake/Kconfig

@@ -20,7 +20,6 @@ config CPU_SPECIFIC_OPTIONS
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select ACPI_NHLT
 	select ARCH_ALL_STAGES_X86_32
-	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS
 	select CPU_INTEL_COMMON

src/soc/intel/tigerlake/Kconfig

@@ -9,7 +9,6 @@ config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select ARCH_ALL_STAGES_X86_32
-	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS
 	select CPU_INTEL_COMMON

src/soc/intel/xeon_sp/Kconfig

@@ -26,7 +26,6 @@ if XEON_SP_COMMON_BASE
 config	CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ARCH_ALL_STAGES_X86_32
-	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CPU_INTEL_COMMON
 	select SOC_INTEL_COMMON