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mainboard/google/brya: Enable tight timestamp 

This change exposes the PCH_INT_ODL line in GPP_F17 as interrupt resource for
CREC device

BUG=none
TEST=manual test

Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I0c05160cb7894b5f7beee93a0c93776f973eae56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Boris Mittelberg 2021-03-25 22:34:28 +00:00 committed by Tim Wawrzynczak
parent 65fce098e3
commit 6c2f80c4a2
2 changed files with 4 additions and 0 deletions
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2
src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h
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@ -64,4 +64,6 @@
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */
#endif /* __BASEBOARD_EC_H__ */ #endif /* __BASEBOARD_EC_H__ */

2
src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h
View File

@ -16,5 +16,7 @@
#define GPIO_EC_IN_RW GPP_F18 #define GPIO_EC_IN_RW GPP_F18
/* Used to gate SoC's SLP_S0# signal */ /* Used to gate SoC's SLP_S0# signal */
#define GPIO_SLP_S0_GATE GPP_F9 #define GPIO_SLP_S0_GATE GPP_F9
/* GPIO IRQ for tight timestamps / wake support */
#define EC_SYNC_IRQ GPP_F17_IRQ
#endif /* __BASEBOARD_GPIO_H__ */ #endif /* __BASEBOARD_GPIO_H__ */