mb/supermicro/x11ssh-tf: configure "POST complete" gpio for IPMI driver
Configure the "POST complete" gpio in the devicetree for the BMC/IPMI driver and set the pad's initial value to 0 since the signal is active- high and shall be set by the IPMI/BMC driver. Also add the pad to early gpio config, since it is expected to have an external pull-up like X11SSM-F, which is wrong and would confuse the BMC. Test: Boot the machine via the BMC web interface and check that sensors get read correctly by the IPMI firmware when the payload starts. Tested successfully. Change-Id: If344b2271bfc8d50b8b64847109818f96f2abbcb Tested-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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3 changed files with 4 additions and 1 deletions
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@ -50,7 +50,7 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_B17, NONE),
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PAD_NC(GPP_B18, NONE),
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PAD_NC(GPP_B19, NONE),
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PAD_CFG_GPO(GPP_B20, 1, PLTRST),
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PAD_CFG_GPO(GPP_B20, 0, PLTRST), /* BMC POST_COMPLETE */
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PAD_NC(GPP_B21, NONE),
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PAD_NC(GPP_B22, NONE),
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PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2),
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@ -14,6 +14,7 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
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PAD_CFG_GPO(GPP_B20, 0, PLTRST), /* BMC POST_COMPLETE */
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};
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void mainboard_configure_early_gpios(void)
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@ -76,6 +76,8 @@ chip soc/intel/skylake
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end
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device pci 1f.0 on # LPC Interface
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chip drivers/ipmi
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use pch_gpio as gpio_dev
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register "post_complete_gpio" = "GPP_B20"
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# On cold boot it takes a while for the BMC to start the IPMI service
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register "wait_for_bmc" = "1"
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register "bmc_boot_timeout" = "60"
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