bootblock: Declare common bootblock_pre_c_entry routine
Enable uses of a common bootblock_pre_c_entry routine. Pass in TSC value as a uint64_t value. TEST=Build for amenia and Galileo Gen2 Change-Id: I8be2e079ababb2cf1f9b7e6293f93e7c778761a1 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15124 Tested-by: build bot (Jenkins) Reviewed-by: Lee Leahy <lpleahyjr@gmail.com>
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@ -29,6 +29,12 @@ void bootblock_mainboard_early_init(void);
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void bootblock_mainboard_init(void);
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void bootblock_mainboard_init(void);
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void bootblock_soc_early_init(void);
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void bootblock_soc_early_init(void);
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void bootblock_soc_init(void);
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void bootblock_soc_init(void);
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/*
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* C code entry point for the boot block.
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*/
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void asmlinkage bootblock_c_entry(uint64_t base_timestamp);
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/*
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/*
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* This is a the same as the bootblock main(), with the difference that it does
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* This is a the same as the bootblock main(), with the difference that it does
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* not collect a timestamp. Instead it accepts the first timestamp as an
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* not collect a timestamp. Instead it accepts the first timestamp as an
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@ -19,7 +19,6 @@
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/mtrr.h>
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#include <device/pci.h>
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#include <device/pci.h>
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#include <lib.h>
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#include <lib.h>
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#include <soc/bootblock.h>
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#include <soc/iomap.h>
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#include <soc/iomap.h>
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#include <soc/cpu.h>
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#include <soc/cpu.h>
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#include <soc/gpio.h>
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#include <soc/gpio.h>
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@ -54,7 +53,7 @@ static void enable_pm_timer(void)
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wrmsr(MSR_EMULATE_PM_TMR, msr);
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wrmsr(MSR_EMULATE_PM_TMR, msr);
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}
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}
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void asmlinkage bootblock_c_entry(uint32_t tsc_hi, uint32_t tsc_lo)
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void asmlinkage bootblock_c_entry(uint64_t base_timestamp)
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{
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{
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device_t dev = NB_DEV_ROOT;
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device_t dev = NB_DEV_ROOT;
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@ -71,7 +70,8 @@ void asmlinkage bootblock_c_entry(uint32_t tsc_hi, uint32_t tsc_lo)
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/* BAR and MMIO enable for IOSF, so that GPIOs can be configured */
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/* BAR and MMIO enable for IOSF, so that GPIOs can be configured */
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_IOSF_BASE_ADDRESS);
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_IOSF_BASE_ADDRESS);
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pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
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pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
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pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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pci_write_config16(dev, PCI_COMMAND,
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PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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/* Decode the ACPI I/O port range for early firmware verification.*/
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/* Decode the ACPI I/O port range for early firmware verification.*/
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dev = PMC_DEV;
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dev = PMC_DEV;
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@ -80,7 +80,7 @@ void asmlinkage bootblock_c_entry(uint32_t tsc_hi, uint32_t tsc_lo)
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PCI_COMMAND_IO | PCI_COMMAND_MASTER);
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PCI_COMMAND_IO | PCI_COMMAND_MASTER);
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/* Call lib/bootblock.c main */
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/* Call lib/bootblock.c main */
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bootblock_main_with_timestamp(((uint64_t)tsc_hi << 32) | tsc_lo);
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bootblock_main_with_timestamp(base_timestamp);
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}
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}
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static void cache_bios_region(void)
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static void cache_bios_region(void)
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@ -130,10 +130,10 @@ before_carstage:
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post_code(0x2b)
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post_code(0x2b)
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/* Restore the timestamp from bootblock_crt0.S (mm2:mm1) */
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/* Restore the timestamp from bootblock_crt0.S (mm2:mm1) */
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movd %mm1, %eax
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push %eax
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movd %mm2, %eax
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movd %mm2, %eax
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push %eax
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push %eax
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movd %mm1, %eax
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push %eax
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/* We can call into C functions now */
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/* We can call into C functions now */
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call bootblock_c_entry
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call bootblock_c_entry
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@ -1,20 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_APOLLOLAKE_BOOTBLOCK_H_
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#define _SOC_APOLLOLAKE_BOOTBLOCK_H_
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#include <arch/cpu.h>
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void asmlinkage bootblock_c_entry(uint32_t tsc_hi, uint32_t tsc_lo);
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#endif
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