cpu: Get rid of unnecessary blank line {before,after} barce
Change-Id: I9b710d279da6db9125519f58ecba109a4d9fa8e3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
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@ -313,7 +313,6 @@ static void generate_P_state_entries(int core, int cores_per_package)
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/* Generate the remaining entries */
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for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
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ratio >= ratio_min; ratio -= ratio_step) {
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/* Calculate power at this ratio */
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power = calculate_power(power_max, ratio_max, ratio);
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clock = ratio * CPU_BCLK;
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@ -217,7 +217,6 @@ static const void *find_cbfs_microcode(void)
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struct ext_sig_entry *entry = (struct ext_sig_entry *)(ext_tbl + 1);
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for (i = 0; i < ext_tbl->ext_sig_cnt; i++, entry++) {
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if ((sig == entry->sig) && (pf & entry->pf)) {
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return ucode_updates;
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}
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@ -185,7 +185,6 @@ static void generate_P_state_entries(int core, int cores_per_package)
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/* Generate the remaining entries */
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for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
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ratio >= ratio_min; ratio -= ratio_step) {
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/* Calculate power at this ratio */
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power = calculate_power(power_max, ratio_max, ratio);
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clock = ratio * IRONLAKE_BCLK + ratio / 3;
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@ -286,7 +286,6 @@ static void generate_P_state_entries(int core, int cores_per_package)
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/* Generate the remaining entries */
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for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
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ratio >= ratio_min; ratio -= ratio_step) {
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/* Calculate power at this ratio */
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power = calculate_power(power_max, ratio_max, ratio);
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clock = ratio * SANDYBRIDGE_BCLK;
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@ -324,7 +324,6 @@ static void model_206ax_report(void)
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static void model_206ax_init(struct device *cpu)
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{
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/* Clear out pending MCEs */
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/* This should only be done on a cold boot */
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mca_clear_status();
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@ -89,7 +89,6 @@ static void configure_misc(void)
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msr = rdmsr(IA32_PECI_CTL);
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msr.lo |= 1;
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wrmsr(IA32_PECI_CTL, msr);
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}
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#define PIC_SENS_CFG 0x1aa
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@ -244,7 +244,6 @@ int read_l2(u32 address)
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/* If OK then get the result from BBL_CR_ADDR */
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msr = rdmsr(BBL_CR_ADDR);
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return (msr.lo >> 0x15);
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}
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/* Write data into the L2 controller register at address */
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@ -270,7 +269,6 @@ int write_l2(u32 address, u32 data)
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*/
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for (i = 0; i < v2; i++) {
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u32 data1, data2;
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// Bits legend
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// data1 = ffffffff
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@ -352,7 +350,6 @@ int calculate_l2_cache_size(void)
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*/
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for (cache_setting = BBLCR3_L2_SIZE_256K;
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cache_setting <= BBLCR3_L2_SIZE_4M; cache_setting <<= 1) {
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eax = bblcr3 | cache_setting;
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msr.lo = eax;
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wrmsr(BBL_CR_CTL3, msr);
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@ -726,7 +723,6 @@ int p6_configure_l2_cache(void)
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/* Write to all cache lines to initialize */
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while (cache_size > 0) {
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/* Each cache line is 32 bytes. */
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cache_size -= 32;
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@ -334,7 +334,6 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu)
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udelay(10);
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}
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}
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static void wait_other_cpus_stop(struct bus *cpu_bus)
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@ -343,7 +343,6 @@ static void commit_fixed_mtrrs(void)
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wrmsr(msr_index[i], fixed_msrs[i]);
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enable_cache();
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fixed_mtrrs_hide_amd_rwdram();
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}
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void x86_setup_fixed_mtrrs_no_enable(void)
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