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cpu: Get rid of unnecessary blank line {before,after} barce 

Change-Id: I9b710d279da6db9125519f58ecba109a4d9fa8e3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This commit is contained in:
Elyes HAOUAS 2022-02-02 18:34:58 +01:00 committed by Felix Singer
parent f551784830
commit 6c42fa20f6
9 changed files with 0 additions and 12 deletions
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1
src/cpu/intel/haswell/acpi.c
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@ -313,7 +313,6 @@ static void generate_P_state_entries(int core, int cores_per_package)
/* Generate the remaining entries */ /* Generate the remaining entries */
for (ratio = ratio_min + ((num_entries - 1) * ratio_step); for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
ratio >= ratio_min; ratio -= ratio_step) { ratio >= ratio_min; ratio -= ratio_step) {
/* Calculate power at this ratio */ /* Calculate power at this ratio */
power = calculate_power(power_max, ratio_max, ratio); power = calculate_power(power_max, ratio_max, ratio);
clock = ratio * CPU_BCLK; clock = ratio * CPU_BCLK;

1
src/cpu/intel/microcode/microcode.c
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@ -217,7 +217,6 @@ static const void *find_cbfs_microcode(void)
struct ext_sig_entry *entry = (struct ext_sig_entry *)(ext_tbl + 1); struct ext_sig_entry *entry = (struct ext_sig_entry *)(ext_tbl + 1);
for (i = 0; i < ext_tbl->ext_sig_cnt; i++, entry++) { for (i = 0; i < ext_tbl->ext_sig_cnt; i++, entry++) {
if ((sig == entry->sig) && (pf & entry->pf)) { if ((sig == entry->sig) && (pf & entry->pf)) {
return ucode_updates; return ucode_updates;
} }

1
src/cpu/intel/model_2065x/acpi.c
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@ -185,7 +185,6 @@ static void generate_P_state_entries(int core, int cores_per_package)
/* Generate the remaining entries */ /* Generate the remaining entries */
for (ratio = ratio_min + ((num_entries - 1) * ratio_step); for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
ratio >= ratio_min; ratio -= ratio_step) { ratio >= ratio_min; ratio -= ratio_step) {
/* Calculate power at this ratio */ /* Calculate power at this ratio */
power = calculate_power(power_max, ratio_max, ratio); power = calculate_power(power_max, ratio_max, ratio);
clock = ratio * IRONLAKE_BCLK + ratio / 3; clock = ratio * IRONLAKE_BCLK + ratio / 3;

1
src/cpu/intel/model_206ax/acpi.c
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@ -286,7 +286,6 @@ static void generate_P_state_entries(int core, int cores_per_package)
/* Generate the remaining entries */ /* Generate the remaining entries */
for (ratio = ratio_min + ((num_entries - 1) * ratio_step); for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
ratio >= ratio_min; ratio -= ratio_step) { ratio >= ratio_min; ratio -= ratio_step) {
/* Calculate power at this ratio */ /* Calculate power at this ratio */
power = calculate_power(power_max, ratio_max, ratio); power = calculate_power(power_max, ratio_max, ratio);
clock = ratio * SANDYBRIDGE_BCLK; clock = ratio * SANDYBRIDGE_BCLK;

1
src/cpu/intel/model_206ax/model_206ax_init.c
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@ -324,7 +324,6 @@ static void model_206ax_report(void)
static void model_206ax_init(struct device *cpu) static void model_206ax_init(struct device *cpu)
{ {
/* Clear out pending MCEs */ /* Clear out pending MCEs */
/* This should only be done on a cold boot */ /* This should only be done on a cold boot */
mca_clear_status(); mca_clear_status();

1
src/cpu/intel/model_6fx/model_6fx_init.c
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@ -89,7 +89,6 @@ static void configure_misc(void)
msr = rdmsr(IA32_PECI_CTL); msr = rdmsr(IA32_PECI_CTL);
msr.lo |= 1; msr.lo |= 1;
wrmsr(IA32_PECI_CTL, msr); wrmsr(IA32_PECI_CTL, msr);
} }
#define PIC_SENS_CFG 0x1aa #define PIC_SENS_CFG 0x1aa

4
src/cpu/intel/slot_1/l2_cache.c
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@ -244,7 +244,6 @@ int read_l2(u32 address)
/* If OK then get the result from BBL_CR_ADDR */ /* If OK then get the result from BBL_CR_ADDR */
msr = rdmsr(BBL_CR_ADDR); msr = rdmsr(BBL_CR_ADDR);
return (msr.lo >> 0x15); return (msr.lo >> 0x15);
} }
/* Write data into the L2 controller register at address */ /* Write data into the L2 controller register at address */
@ -270,7 +269,6 @@ int write_l2(u32 address, u32 data)
*/ */
for (i = 0; i < v2; i++) { for (i = 0; i < v2; i++) {
u32 data1, data2; u32 data1, data2;
// Bits legend // Bits legend
// data1 = ffffffff // data1 = ffffffff
@ -352,7 +350,6 @@ int calculate_l2_cache_size(void)
*/ */
for (cache_setting = BBLCR3_L2_SIZE_256K; for (cache_setting = BBLCR3_L2_SIZE_256K;
cache_setting <= BBLCR3_L2_SIZE_4M; cache_setting <<= 1) { cache_setting <= BBLCR3_L2_SIZE_4M; cache_setting <<= 1) {
eax = bblcr3 | cache_setting; eax = bblcr3 | cache_setting;
msr.lo = eax; msr.lo = eax;
wrmsr(BBL_CR_CTL3, msr); wrmsr(BBL_CR_CTL3, msr);
@ -726,7 +723,6 @@ int p6_configure_l2_cache(void)
/* Write to all cache lines to initialize */ /* Write to all cache lines to initialize */
while (cache_size > 0) { while (cache_size > 0) {
/* Each cache line is 32 bytes. */ /* Each cache line is 32 bytes. */
cache_size -= 32; cache_size -= 32;

1
src/cpu/x86/lapic/lapic_cpu_init.c
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@ -334,7 +334,6 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu)
udelay(10); udelay(10);
} }
} }
static void wait_other_cpus_stop(struct bus *cpu_bus) static void wait_other_cpus_stop(struct bus *cpu_bus)

1
src/cpu/x86/mtrr/mtrr.c
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@ -343,7 +343,6 @@ static void commit_fixed_mtrrs(void)
wrmsr(msr_index[i], fixed_msrs[i]); wrmsr(msr_index[i], fixed_msrs[i]);
enable_cache(); enable_cache();
fixed_mtrrs_hide_amd_rwdram(); fixed_mtrrs_hide_amd_rwdram();
} }
void x86_setup_fixed_mtrrs_no_enable(void) void x86_setup_fixed_mtrrs_no_enable(void)