amdfwtool: Add options to support mainboard specific SPL table
For the generic board which uses Cezanne, we use the generic SPL table. For the Guybrush Chromebook, we need to use a customized SPL file. BUG=b:216096562 Change-Id: I385b0fe13cb78a053c07127ec3ea1c61dc42c7e4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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@ -642,6 +642,7 @@ static void free_psp_firmware_filenames(amd_fw_entry *fw_table)
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if (index->filename &&
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if (index->filename &&
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index->type != AMD_FW_VERSTAGE_SIG &&
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index->type != AMD_FW_VERSTAGE_SIG &&
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index->type != AMD_FW_PSP_VERSTAGE &&
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index->type != AMD_FW_PSP_VERSTAGE &&
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index->type != AMD_FW_SPL &&
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index->type != AMD_FW_PSP_WHITELIST) {
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index->type != AMD_FW_PSP_WHITELIST) {
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free(index->filename);
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free(index->filename);
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}
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}
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@ -1086,6 +1087,7 @@ enum {
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AMDFW_OPT_USE_PSPSECUREOS,
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AMDFW_OPT_USE_PSPSECUREOS,
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AMDFW_OPT_LOAD_MP2FW,
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AMDFW_OPT_LOAD_MP2FW,
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AMDFW_OPT_LOAD_S0I3,
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AMDFW_OPT_LOAD_S0I3,
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AMDFW_OPT_SPL_TABLE,
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AMDFW_OPT_VERSTAGE,
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AMDFW_OPT_VERSTAGE,
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AMDFW_OPT_VERSTAGE_SIG,
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AMDFW_OPT_VERSTAGE_SIG,
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@ -1131,6 +1133,7 @@ static struct option long_options[] = {
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{"use-pspsecureos", no_argument, 0, AMDFW_OPT_USE_PSPSECUREOS },
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{"use-pspsecureos", no_argument, 0, AMDFW_OPT_USE_PSPSECUREOS },
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{"load-mp2-fw", no_argument, 0, AMDFW_OPT_LOAD_MP2FW },
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{"load-mp2-fw", no_argument, 0, AMDFW_OPT_LOAD_MP2FW },
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{"load-s0i3", no_argument, 0, AMDFW_OPT_LOAD_S0I3 },
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{"load-s0i3", no_argument, 0, AMDFW_OPT_LOAD_S0I3 },
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{"spl-table", required_argument, 0, AMDFW_OPT_SPL_TABLE },
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{"verstage", required_argument, 0, AMDFW_OPT_VERSTAGE },
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{"verstage", required_argument, 0, AMDFW_OPT_VERSTAGE },
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{"verstage_sig", required_argument, 0, AMDFW_OPT_VERSTAGE_SIG },
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{"verstage_sig", required_argument, 0, AMDFW_OPT_VERSTAGE_SIG },
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/* BIOS Directory Table items */
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/* BIOS Directory Table items */
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@ -1463,6 +1466,11 @@ int main(int argc, char **argv)
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case AMDFW_OPT_LOAD_S0I3:
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case AMDFW_OPT_LOAD_S0I3:
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cb_config.s0i3 = true;
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cb_config.s0i3 = true;
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break;
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break;
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case AMDFW_OPT_SPL_TABLE:
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register_fw_filename(AMD_FW_SPL, sub, optarg);
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sub = instance = 0;
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cb_config.have_mb_spl = true;
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break;
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case AMDFW_OPT_WHITELIST:
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case AMDFW_OPT_WHITELIST:
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register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg);
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register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg);
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sub = instance = 0;
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sub = instance = 0;
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@ -251,6 +251,7 @@ typedef struct _amd_cb_config {
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bool load_mp2_fw;
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bool load_mp2_fw;
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bool multi_level;
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bool multi_level;
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bool s0i3;
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bool s0i3;
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bool have_mb_spl;
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} amd_cb_config;
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} amd_cb_config;
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void register_fw_fuse(char *str);
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void register_fw_fuse(char *str);
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@ -283,8 +283,12 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename,
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fw_type = AMD_FW_KEYDB_TOS;
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fw_type = AMD_FW_KEYDB_TOS;
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subprog = 0;
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subprog = 0;
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} else if (strcmp(fw_name, "SPL_TABLE_FILE") == 0) {
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} else if (strcmp(fw_name, "SPL_TABLE_FILE") == 0) {
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if (cb_config->have_mb_spl) {
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fw_type = AMD_FW_SPL;
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fw_type = AMD_FW_SPL;
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subprog = 0;
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subprog = 0;
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} else {
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fw_type = AMD_FW_SKIP;
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}
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} else if (strcmp(fw_name, "DMCUERAMDCN21_FILE") == 0) {
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} else if (strcmp(fw_name, "DMCUERAMDCN21_FILE") == 0) {
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fw_type = AMD_FW_DMCU_ERAM;
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fw_type = AMD_FW_DMCU_ERAM;
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subprog = 0;
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subprog = 0;
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