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amdfwtool: Add options to support mainboard specific SPL table 

For the generic board which uses Cezanne, we use the generic SPL
table. For the Guybrush Chromebook, we need to use a customized SPL
file.

BUG=b:216096562

Change-Id: I385b0fe13cb78a053c07127ec3ea1c61dc42c7e4
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Zheng Bao 2022-02-11 11:51:26 +08:00 committed by Felix Held
parent 39cf79900f
commit 6c5ec8e31c
3 changed files with 15 additions and 2 deletions
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8
util/amdfwtool/amdfwtool.c
View File

@ -642,6 +642,7 @@ static void free_psp_firmware_filenames(amd_fw_entry *fw_table)
if (index->filename && if (index->filename &&
index->type != AMD_FW_VERSTAGE_SIG && index->type != AMD_FW_VERSTAGE_SIG &&
index->type != AMD_FW_PSP_VERSTAGE && index->type != AMD_FW_PSP_VERSTAGE &&
index->type != AMD_FW_SPL &&
index->type != AMD_FW_PSP_WHITELIST) { index->type != AMD_FW_PSP_WHITELIST) {
free(index->filename); free(index->filename);
} }
@ -1086,6 +1087,7 @@ enum {
AMDFW_OPT_USE_PSPSECUREOS, AMDFW_OPT_USE_PSPSECUREOS,
AMDFW_OPT_LOAD_MP2FW, AMDFW_OPT_LOAD_MP2FW,
AMDFW_OPT_LOAD_S0I3, AMDFW_OPT_LOAD_S0I3,
AMDFW_OPT_SPL_TABLE,
AMDFW_OPT_VERSTAGE, AMDFW_OPT_VERSTAGE,
AMDFW_OPT_VERSTAGE_SIG, AMDFW_OPT_VERSTAGE_SIG,
@ -1131,6 +1133,7 @@ static struct option long_options[] = {
{"use-pspsecureos", no_argument, 0, AMDFW_OPT_USE_PSPSECUREOS }, {"use-pspsecureos", no_argument, 0, AMDFW_OPT_USE_PSPSECUREOS },
{"load-mp2-fw", no_argument, 0, AMDFW_OPT_LOAD_MP2FW }, {"load-mp2-fw", no_argument, 0, AMDFW_OPT_LOAD_MP2FW },
{"load-s0i3", no_argument, 0, AMDFW_OPT_LOAD_S0I3 }, {"load-s0i3", no_argument, 0, AMDFW_OPT_LOAD_S0I3 },
{"spl-table", required_argument, 0, AMDFW_OPT_SPL_TABLE },
{"verstage", required_argument, 0, AMDFW_OPT_VERSTAGE }, {"verstage", required_argument, 0, AMDFW_OPT_VERSTAGE },
{"verstage_sig", required_argument, 0, AMDFW_OPT_VERSTAGE_SIG }, {"verstage_sig", required_argument, 0, AMDFW_OPT_VERSTAGE_SIG },
/* BIOS Directory Table items */ /* BIOS Directory Table items */
@ -1463,6 +1466,11 @@ int main(int argc, char **argv)
case AMDFW_OPT_LOAD_S0I3: case AMDFW_OPT_LOAD_S0I3:
cb_config.s0i3 = true; cb_config.s0i3 = true;
break; break;
case AMDFW_OPT_SPL_TABLE:
register_fw_filename(AMD_FW_SPL, sub, optarg);
sub = instance = 0;
cb_config.have_mb_spl = true;
break;
case AMDFW_OPT_WHITELIST: case AMDFW_OPT_WHITELIST:
register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg); register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg);
sub = instance = 0; sub = instance = 0;

1
util/amdfwtool/amdfwtool.h
View File

@ -251,6 +251,7 @@ typedef struct _amd_cb_config {
bool load_mp2_fw; bool load_mp2_fw;
bool multi_level; bool multi_level;
bool s0i3; bool s0i3;
bool have_mb_spl;
} amd_cb_config; } amd_cb_config;
void register_fw_fuse(char *str); void register_fw_fuse(char *str);

8
util/amdfwtool/data_parse.c
View File

@ -283,8 +283,12 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename,
fw_type = AMD_FW_KEYDB_TOS; fw_type = AMD_FW_KEYDB_TOS;
subprog = 0; subprog = 0;
} else if (strcmp(fw_name, "SPL_TABLE_FILE") == 0) { } else if (strcmp(fw_name, "SPL_TABLE_FILE") == 0) {
fw_type = AMD_FW_SPL; if (cb_config->have_mb_spl) {
subprog = 0; fw_type = AMD_FW_SPL;
subprog = 0;
} else {
fw_type = AMD_FW_SKIP;
}
} else if (strcmp(fw_name, "DMCUERAMDCN21_FILE") == 0) { } else if (strcmp(fw_name, "DMCUERAMDCN21_FILE") == 0) {
fw_type = AMD_FW_DMCU_ERAM; fw_type = AMD_FW_DMCU_ERAM;
subprog = 0; subprog = 0;