diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 8847d88f93..df4ac6046a 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -52,12 +52,14 @@ chip soc/intel/alderlake
 		.flags = PCIE_RP_CLK_REQ_DETECT,
 	}"
 
-	# Enable PCH PCIE RP 8 using free running CLK (0x80)
-	# Clock source is shared with LAN and hence marked as free running.
+	# NOTE: requires GPP_A7 set to Native Function 1 for SRCCLK_OE7
 	register "pch_pcie_rp[PCH_RP(8)]" = "{
-		.flags = PCIE_RP_CLK_SRC_UNUSED,
+                .clk_src = 7,
+                .clk_req = 7,
+                .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
+                .PcieRpL1Substates = L1_SS_L1_2,
+		.pcie_rp_detect_timeout_ms = 50,
 	}"
-	register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
 
 	# Enable PCH PCIE RP 9 using CLK 1
 	register "pch_pcie_rp[PCH_RP(9)]" = "{
diff --git a/src/mainboard/intel/adlrvp/early_gpio.c b/src/mainboard/intel/adlrvp/early_gpio.c
index 57cadfade8..af933ebd8a 100644
--- a/src/mainboard/intel/adlrvp/early_gpio.c
+++ b/src/mainboard/intel/adlrvp/early_gpio.c
@@ -18,6 +18,15 @@ static const struct pad_config early_gpio_table[] = {
 	/* EC_IN_RW */
 	PAD_CFG_GPI(GPP_E7, NONE, DEEP),
 
+	/* x4 PCIE slot 1 RESET */
+	PAD_CFG_GPO(GPP_F10, 0, PLTRST),
+
+	/* Support external source clock via OEB6 and OEB7 */
+	/* SRCCLK_OEB6 for built-in LAN */
+	PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF2),
+	/* SRCCLK_OEB7 for x4 slot */
+	PAD_CFG_NF(GPP_A7, NONE, PLTRST, NF1),
+
 	/* CPU PCIe VGPIO for RP0 */
 	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, PLTRST, NF1),
 	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, PLTRST, NF1),
diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c
index 92a8c30420..e4483d2257 100644
--- a/src/mainboard/intel/adlrvp/gpio.c
+++ b/src/mainboard/intel/adlrvp/gpio.c
@@ -67,10 +67,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_B4, 1, PLTRST),
 	/* M.2_PCH_SSD_PWREN */
 	PAD_CFG_GPO(GPP_D16, 1, PLTRST),
-	/* SRCCLK_OEB7 */
-	PAD_CFG_GPO(GPP_A7, 0, PLTRST),
-	/* SRCCLK_OEB6 */
-	PAD_CFG_GPO(GPP_E5, 0, PLTRST),
 
 	/* CAM1_RST */
 	PAD_CFG_GPO(GPP_R5, 1, PLTRST),
@@ -189,8 +185,6 @@ static const struct pad_config gpio_table[] = {
 	/* I2S0_RXD */
 	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
 
-	/* I2S2_SCLK */
-	PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
 	/* I2S2_SFRM */
 	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
 	/* I2S2_TXD */