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mb/google/puff/var/*: Set LAN/WLAN device type to generic 

Change the LAN/WiFi device types from PCI to generic, so that the bogus
PCI device and function values don't end up in coreboot's internal
device tree. The presence of these bogus PCI devices cause the LPI
constraint generator to create a reference for an ACPI device which does
not exist (SB.PCI0.RP{xx}.MCHC). The invalid reference(s) cause a
Windows BSOD (INTERNAL_POWER_ERROR).

TEST=build/boot Win11 on google/puff (wyvern). Verify LAN/WLAN devices
function correctly under Windows and Linux.

Change-Id: Ibc5f96250edb358d0517bd3840bf5604defe0b39
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This commit is contained in:
Matt DeVillier 2023-11-01 15:52:03 -05:00 committed by Matt DeVillier
parent 3c83995ff9
commit 6c705e766f
11 changed files with 11 additions and 11 deletions
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2
src/mainboard/google/puff/variants/ambassador/overridetree.cb
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@ -396,7 +396,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0"
register "enable_aspm_l1_2" = "1"
device pci 00.0 on end
device generic 0 on end
end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC

2
src/mainboard/google/puff/variants/baseboard/devicetree.cb
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@ -323,7 +323,7 @@ chip soc/intel/cannonlake
device pci 1d.5 on
chip drivers/wifi/generic
register "wake" = "GPE0_DW1_01"
device pci 00.0 on end
device generic 0 on end
end
register "PcieRpSlotImplemented[13]" = "1"
end # PCI Express Port 14 (x4)

2
src/mainboard/google/puff/variants/duffy/overridetree.cb
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@ -455,7 +455,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0"
register "enable_aspm_l1_2" = "1"
device pci 00.0 on end
device generic 0 on end
end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC

2
src/mainboard/google/puff/variants/faffy/overridetree.cb
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@ -429,7 +429,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0"
register "enable_aspm_l1_2" = "1"
device pci 00.0 on end
device generic 0 on end
end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC

2
src/mainboard/google/puff/variants/genesis/overridetree.cb
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@ -426,7 +426,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0"
register "enable_aspm_l1_2" = "1"
device pci 00.0 on end
device generic 0 on end
end
end
device pci 1c.7 on # PCI Root Port 8 (WLAN)

2
src/mainboard/google/puff/variants/kaisa/overridetree.cb
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@ -455,7 +455,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0"
register "enable_aspm_l1_2" = "1"
device pci 00.0 on end
device generic 0 on end
end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC

2
src/mainboard/google/puff/variants/moonbuggy/overridetree.cb
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@ -428,7 +428,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0"
register "enable_aspm_l1_2" = "1"
device pci 00.0 on end
device generic 0 on end
end
end
device pci 1c.7 on # PCI Root Port 8 (WLAN)

2
src/mainboard/google/puff/variants/noibat/overridetree.cb
View File

@ -366,7 +366,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0"
register "enable_aspm_l1_2" = "1"
device pci 00.0 on end
device generic 0 on end
end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC

2
src/mainboard/google/puff/variants/puff/overridetree.cb
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@ -390,7 +390,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0"
register "enable_aspm_l1_2" = "1"
device pci 00.0 on end
device generic 0 on end
end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC

2
src/mainboard/google/puff/variants/scout/overridetree.cb
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@ -406,7 +406,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0"
register "enable_aspm_l1_2" = "1"
device pci 00.0 on end
device generic 0 on end
end
end
device pci 1c.7 on # PCI Root Port 8 (WLAN)

2
src/mainboard/google/puff/variants/wyvern/overridetree.cb
View File

@ -391,7 +391,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0"
register "enable_aspm_l1_2" = "1"
device pci 00.0 on end
device generic 0 on end
end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC