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mb/siemens/{baseboard,mc_apl3,mc_apl4,mc_apl5}: Fix GPIO_168 

This GPIO is corrected with reference to the Apollo Lake SoC EDS Vol 4
revision 2.4 chapter 10.1.2.3 List of Pins that are GPIOs but cannot be
used in Function 0 (GPIO) mode.

Change-Id: I98628ade3a1e19730ca6e6b4a63c28e6816176ce
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Mario Scheithauer 2019-07-10 14:34:50 +02:00 committed by Martin Roth
parent 1f21a96c84
commit 6c7857411c
4 changed files with 4 additions and 4 deletions
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2
src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c
View File

@ -49,7 +49,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), /* SDIO_CLK */ PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), /* SDIO_CLK */
PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* SDIO_D0 */ PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* SDIO_D0 */
/* Configure SDIO to enable power gating. */ /* Configure SDIO to enable power gating. */
PAD_CFG_GPI(GPIO_168, NONE, DEEP), /* SDIO_D1 */ PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), /* SDIO_D1 */
PAD_CFG_GPI(GPIO_169, NONE, DEEP), /* SDIO_D2 */ PAD_CFG_GPI(GPIO_169, NONE, DEEP), /* SDIO_D2 */
PAD_CFG_GPI(GPIO_170, NONE, DEEP), /* SDIO_D3 */ PAD_CFG_GPI(GPIO_170, NONE, DEEP), /* SDIO_D3 */
PAD_CFG_GPI(GPIO_171, NONE, DEEP), /* SDIO_CMD */ PAD_CFG_GPI(GPIO_171, NONE, DEEP), /* SDIO_CMD */

2
src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c
View File

@ -49,7 +49,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), /* SDIO_CLK */ PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), /* SDIO_CLK */
PAD_CFG_GPI(GPIO_167, UP_20K, DEEP), /* SDIO_D0 */ PAD_CFG_GPI(GPIO_167, UP_20K, DEEP), /* SDIO_D0 */
/* Configure SDIO to enable power gating. */ /* Configure SDIO to enable power gating. */
PAD_CFG_GPI(GPIO_168, UP_20K, DEEP), /* SDIO_D1 */ PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), /* SDIO_D1 */
PAD_CFG_GPI(GPIO_169, UP_20K, DEEP), /* SDIO_D2 */ PAD_CFG_GPI(GPIO_169, UP_20K, DEEP), /* SDIO_D2 */
PAD_CFG_GPI(GPIO_170, UP_20K, DEEP), /* SDIO_D3 */ PAD_CFG_GPI(GPIO_170, UP_20K, DEEP), /* SDIO_D3 */
PAD_CFG_GPI(GPIO_171, UP_20K, DEEP), /* SDIO_CMD */ PAD_CFG_GPI(GPIO_171, UP_20K, DEEP), /* SDIO_CMD */

2
src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c
View File

@ -47,7 +47,7 @@ static const struct pad_config gpio_table[] = {
/* SDIO - unused */ /* SDIO - unused */
PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), PAD_CFG_GPI(GPIO_166, DN_20K, DEEP),
PAD_CFG_GPI(GPIO_167, DN_20K, DEEP), PAD_CFG_GPI(GPIO_167, DN_20K, DEEP),
PAD_CFG_GPI(GPIO_168, DN_20K, DEEP), PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1),
PAD_CFG_GPI(GPIO_169, DN_20K, DEEP), PAD_CFG_GPI(GPIO_169, DN_20K, DEEP),
PAD_CFG_GPI(GPIO_170, DN_20K, DEEP), PAD_CFG_GPI(GPIO_170, DN_20K, DEEP),
PAD_CFG_GPI(GPIO_171, DN_20K, DEEP), PAD_CFG_GPI(GPIO_171, DN_20K, DEEP),

2
src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c
View File

@ -49,7 +49,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), /* SDIO_CLK */ PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), /* SDIO_CLK */
PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* SDIO_D0 */ PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* SDIO_D0 */
/* Configure SDIO to enable power gating. */ /* Configure SDIO to enable power gating. */
PAD_CFG_GPI(GPIO_168, NONE, DEEP), /* SDIO_D1 */ PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), /* SDIO_D1 */
PAD_CFG_GPI(GPIO_169, NONE, DEEP), /* SDIO_D2 */ PAD_CFG_GPI(GPIO_169, NONE, DEEP), /* SDIO_D2 */
PAD_CFG_GPI(GPIO_170, NONE, DEEP), /* SDIO_D3 */ PAD_CFG_GPI(GPIO_170, NONE, DEEP), /* SDIO_D3 */
PAD_CFG_GPI(GPIO_171, NONE, DEEP), /* SDIO_CMD */ PAD_CFG_GPI(GPIO_171, NONE, DEEP), /* SDIO_CMD */