From 6c887544bbfa3b834fa30536d9535898f09549d5 Mon Sep 17 00:00:00 2001 From: Tao Xia Date: Tue, 27 Jul 2021 17:39:12 +0800 Subject: [PATCH] mb/google/dedede/var/storo: Set the xHCI LFPS period sampling off time to 0ms LTE module L850-GL may encounter U3 wakeup race condition with the host. Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not miss the device-initiated U3 wakeup thus avoid the race condition. BUG=b:193898133 BRANCH=dedede TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0: iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Tao Xia Change-Id: Ic84dc83b749cf3c6029a06730096b64ef8cb8cd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56626 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/dedede/variants/storo/overridetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb index e8246522b9..aedb285d36 100644 --- a/src/mainboard/google/dedede/variants/storo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb @@ -79,6 +79,8 @@ chip soc/intel/jasperlake register "tcc_offset" = "10" # TCC of 95C + register "xhci_lfps_sampling_offtime_ms" = "0" + device domain 0 on device pci 04.0 on chip drivers/intel/dptf