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cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size() 

This patch helps to generate correct MTRR mask value while
using set_var_mtrr().

example:
set_var_mtrr(1, 0x99000000, 16*MiB, WP)

without CL :
0x0000000099000005: PHYBASE2: Address = 0x0000000099000000, WP
0x0000000fff000800: PHYMASK2: Length  = 0x0000007001000000, Valid

with CL :
0x0000000099000005: PHYBASE1: Address = 0x0000000099000000, WP
0x0000007fff000800: PHYMASK1: Length  = 0x0000000001000000, Valid

Change-Id: Ie3185dd8d4af73ec0605e19e9aa4223f2c2ad462
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34753
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2019-08-07 08:54:15 +05:30
parent 41d9b65149
commit 6c8a040ec5
1 changed files with 2 additions and 1 deletions
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3
src/cpu/x86/mtrr/earlymtrr.c
View File

@ -11,6 +11,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <cpu/cpu.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
@ -51,6 +52,6 @@ void set_var_mtrr(
basem.hi = 0; basem.hi = 0;
wrmsr(MTRR_PHYS_BASE(reg), basem); wrmsr(MTRR_PHYS_BASE(reg), basem);
maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1;
wrmsr(MTRR_PHYS_MASK(reg), maskm); wrmsr(MTRR_PHYS_MASK(reg), maskm);
} }