drivers/intel/fsp2_0: Add new config option to support FSP CAR
CPU_MICROCODE_CBFS_LEN and CPU_MICROCODE_CBFS_LOC configs pass the CPU microcode length and base address in CBFS to FSPT binary as init parameters. Add new config FSP_T_XIP in Kconfig, which is selected by platform config. If FSP_T_XIP is selected, then relocate FSPT binary while adding it in CBFS so that it can be executed in place. BUG= None TEST= Build for both CFL RVP11 & RVP8 and verified for successfull CAR setup. Change-Id: Ic46e0bb9ee13c38ff322979119c4813653c61029 Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/28985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -53,6 +53,21 @@ config DISPLAY_UPD_DATA
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Display the user specified product data prior to memory
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initialization.
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config CPU_MICROCODE_CBFS_LEN
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hex "Microcode update region length in bytes"
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depends on FSP_CAR
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default 0x0
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help
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The length in bytes of the microcode update region.
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config CPU_MICROCODE_CBFS_LOC
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hex "Microcode update base address in CBFS"
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depends on FSP_CAR
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default 0x0
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help
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The location (base address) in CBFS that contains the
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microcode update binary.
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config FSP_T_CBFS
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string "Name of FSP-T in CBFS"
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depends on FSP_CAR
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@ -109,6 +124,12 @@ config FSP_M_XIP
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help
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Select this value when FSP-M is execute-in-place.
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config FSP_T_XIP
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bool
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default n
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help
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Select this value when FSP-T is execute-in-place.
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config FSP_USES_CB_STACK
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bool
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default n
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@ -52,6 +52,9 @@ CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include
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cbfs-files-$(CONFIG_FSP_CAR) += $(CONFIG_FSP_T_CBFS)
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$(CONFIG_FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE))
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$(CONFIG_FSP_T_CBFS)-type := fsp
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ifeq ($(CONFIG_FSP_T_XIP),y)
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$(CONFIG_FSP_T_CBFS)-options := --xip
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endif
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cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS)
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$(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE))
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