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libpayload: read register width from coreboot table 

Some SOCs (like pistachio, for instance) provide an 8250 compatible
UART, which has the same register layout, but mapped to a bus of a
different width.

Instead of adding a new driver for these controllers, it is better to
have coreboot report UART register width to libpayload, and have it
adjust the offsets accordingly when accessing the UART.

BRANCH=none
BUG=chrome-os-partner:31438
TEST=with the rest of the patches integrated depthcharge console messages
     show up when running on the FPGA board

Change-Id: I05891a9471a5369d3bfafe90cd0c9b0a7e5a667e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42
Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240027
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9739
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Vadim Bendebury 2015-01-09 16:54:19 -08:00 committed by Patrick Georgi
parent 9dccf1c40b
commit 6cc5e52ec6
2 changed files with 5 additions and 0 deletions
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4
payloads/libpayload/drivers/serial/8250.c
View File

@ -39,6 +39,8 @@ static int serial_is_mem_mapped = 0;
static uint8_t serial_read_reg(int offset)
{
offset *= lib_sysinfo.serial->regwidth;
#ifdef CONFIG_LP_IO_ADDRESS_SPACE
if (!serial_is_mem_mapped)
return inb(IOBASE + offset);
@ -49,6 +51,8 @@ static uint8_t serial_read_reg(int offset)
static void serial_write_reg(uint8_t val, int offset)
{
offset *= lib_sysinfo.serial->regwidth;
#ifdef CONFIG_LP_IO_ADDRESS_SPACE
if (!serial_is_mem_mapped)
outb(val, IOBASE + offset);

1
payloads/libpayload/include/coreboot_tables.h
View File

@ -120,6 +120,7 @@ struct cb_serial {
u32 type;
u32 baseaddr;
u32 baud;
u32 regwidth;
};
#define CB_TAG_CONSOLE 0x00010