vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.2
Update FSP header files to match FSP Reference Code Release v2.0.2 for Gemimilake CQ-DEPEND=CL:*594651,CL:*598345 Change-Id: I78d064db41a54d97e98d6e44e0832724127e5bfc Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/25757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -993,7 +993,12 @@ typedef struct {
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**/
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UINT32 RootPort5Perst;
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/** Offset 0x017C
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/** Offset 0x017C - CpuPeiApWakeupBufferAddr
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Address for CpuPeiApWakeupBuffer.
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**/
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UINT32 CpuPeiApWakeupBufferAddr;
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/** Offset 0x0180
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**/
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UINT8 ReservedFspmUpd[4];
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} FSP_M_CONFIG;
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@ -1014,9 +1019,9 @@ typedef struct {
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**/
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FSP_M_CONFIG FspmConfig;
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/** Offset 0x0180
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/** Offset 0x0184
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**/
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UINT8 UnusedUpdSpace1[134];
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UINT8 UnusedUpdSpace1[130];
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/** Offset 0x0206
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**/
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@ -1701,11 +1701,72 @@ typedef struct {
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**/
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UINT8 ProcessorTraceOutputScheme;
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/** Offset 0x03A9
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/** Offset 0x03A9 - USB PDO Programming
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Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
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during later phase. 1: enable, 0: disable
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1: enable, 0: disable
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**/
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UINT8 ReservedFspsUpd[7];
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UINT8 UsbPdoProgramming;
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/** Offset 0x03AA
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**/
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UINT8 ReservedFspsUpd[6];
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} FSP_S_CONFIG;
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/** Fsp S SGX Configuration
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**/
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typedef struct {
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/** Offset 0x03C0
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**/
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UINT32 Signature;
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/** Offset 0x03C4 - Selective enable SGX
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Selective enable SGX. 0xFFFF(Default).
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**/
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UINT16 SelectiveEnableSgx;
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/** Offset 0x03C6 - SGX debug mode
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Select SGX mode. 0:Disable(default), 1:Enable
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0:Disable(default), 1:Enable
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**/
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UINT8 SgxDebugMode;
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/** Offset 0x03C7 - SGX Launch Control Policy Mode
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Select Launch Control Policy Mode. 0:Intel - Default, 1:Per-boot Select mode(default)
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0:Intel locked , 1:Unlocked mode(default) , 2: Locked mode
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**/
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UINT8 SgxLcp;
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/** Offset 0x03C8 - LE KeyHash0
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LE KeyHash0. 0x0(Default).
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**/
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UINT64 SgxLePubKeyHash0;
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/** Offset 0x03D0 - LE KeyHash1
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LE KeyHash1. 0x0(Default).
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**/
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UINT64 SgxLePubKeyHash1;
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/** Offset 0x03D8 - LE KeyHash2
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LE KeyHash2. 0x0(Default).
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**/
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UINT64 SgxLePubKeyHash2;
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/** Offset 0x03E0
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**/
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UINT8 UnusedUpdSpace8[16];
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/** Offset 0x03F0 - LE KeyHash3
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LE KeyHash3. 0x0(Default).
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**/
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UINT64 SgxLePubKeyHash3;
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/** Offset 0x03F8
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**/
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UINT8 ReservedFspsSgxUpd[6];
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} FSP_S_SGX_CONFIG;
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/** Fsp S UPD Configuration
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**/
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typedef struct {
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@ -1720,7 +1781,11 @@ typedef struct {
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/** Offset 0x03B0
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**/
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UINT8 UnusedUpdSpace7[78];
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UINT8 UnusedUpdSpace7[16];
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/** Offset 0x03C0
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**/
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FSP_S_SGX_CONFIG FspsSgxConfig;
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/** Offset 0x03FE
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**/
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