diff --git a/src/mainboard/dell/s1850/Kconfig b/src/mainboard/dell/s1850/Kconfig
index ddad72c6f0..eeb57885de 100644
--- a/src/mainboard/dell/s1850/Kconfig
+++ b/src/mainboard/dell/s1850/Kconfig
@@ -1,5 +1,5 @@
 config BOARD_DELL_S1850
-	bool "S1850"
+	bool "PowerEdge 1850"
 	select ARCH_X86
 	select CPU_INTEL_SOCKET_MPGA604
 	select NORTHBRIDGE_INTEL_E7520
@@ -8,7 +8,7 @@ config BOARD_DELL_S1850
 	select SUPERIO_NSC_PC8374
 	select PIRQ_TABLE
 	help
-	  Dell S1850 mainboard.
+	  Dell PowerEdge 1850 mainboard.
 
 config MAINBOARD_DIR
 	string
diff --git a/targets/motorola/sandpoint/Config.lb b/targets/motorola/sandpoint/Config.lb
deleted file mode 100644
index 473b27a28b..0000000000
--- a/targets/motorola/sandpoint/Config.lb
+++ /dev/null
@@ -1,31 +0,0 @@
-# Sample config file for Motorola Sandpoint X3 Demo Board with
-# the Altimus mpc7410 PMC card
-# This will make a target directory of ./sandpoint
-
-target sandpoint
-
-mainboard motorola/sandpointx3_altimus_mpc7410
-
-# Sandpoint Demo Board
-romimage "fallback"
-	## Base of ROM
-	option CONFIG_ROMBASE=0xfff00000
-
-	## Sandpoint reset vector
-	option CONFIG_RESET=CONFIG_ROMBASE+0x100
-
-	## Exception vectors (other than reset vector)
-	option CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100
-
-	## Start of coreboot in the boot rom
-	## = CONFIG_RESET + exeception vector table size
-	option CONFIG_ROMSTART=CONFIG_RESET+0x3100
-
-	## Coreboot C code runs at this location in RAM
-	option CONFIG_RAMBASE=0x00100000
-	option CONFIG_RAMSTART=0x00100000
-
-	option CONFIG_SANDPOINT_ALTIMUS=1
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/motorola/sandpoint/Config.lb.ide_stream b/targets/motorola/sandpoint/Config.lb.ide_stream
deleted file mode 100644
index 79aa44c38f..0000000000
--- a/targets/motorola/sandpoint/Config.lb.ide_stream
+++ /dev/null
@@ -1,90 +0,0 @@
-# Sample config file for Motorola Sandpoint X3 Demo Board with
-# the Altimus mpc7410 PMC card
-# This will make a target directory of ./sandpoint
-
-loadoptions
-
-target sandpoint
-
-uses CONFIG_CROSS_COMPILE 
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_SANDPOINT_ALTIMUS 
-uses CONFIG_COMPRESS 
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL 
-uses CONFIG_USE_INIT
-uses CONFIG_CHIP_CONFIGURE
-uses CONFIG_NO_POST
-uses CONFIG_CONSOLE_SERIAL8250 
-uses CONFIG_TTYS0_BASE 
-uses CONFIG_IDE_PAYLOAD 
-uses CONFIG_IDE_BOOT_DRIVE
-uses CONFIG_IDE_SWAB CONFIG_IDE_OFFSET 
-uses CONFIG_ROM_SIZE
-uses CONFIG_RESET
-uses CONFIG_EXCEPTION_VECTORS
-uses CONFIG_ROMBASE
-uses CONFIG_ROMSTART
-uses CONFIG_RAMBASE
-uses CONFIG_RAMSTART
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-
-## use a cross compiler
-#option CONFIG_CROSS_COMPILE="powerpc-eabi-"
-#option CONFIG_CROSS_COMPILE="ppc_74xx-"
-
-## Use stage 1 initialization code
-option CONFIG_USE_INIT=1
-
-## Use static configuration
-option CONFIG_CHIP_CONFIGURE=1
-
-## We don't use compressed image
-option CONFIG_COMPRESS=0
-
-## Turn off POST codes
-option CONFIG_NO_POST=1
-
-## Enable serial console
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-option CONFIG_CONSOLE_SERIAL8250=1
-option CONFIG_TTYS0_BASE=0x3f8
-
-## Boot linux from IDE
-option CONFIG_IDE_PAYLOAD=1
-option CONFIG_IDE_BOOT_DRIVE=0
-option CONFIG_IDE_SWAB=1
-option CONFIG_IDE_OFFSET=0
-
-# ROM is 1Mb
-option CONFIG_ROM_SIZE=1024*1024
-
-# Set stack and heap sizes (stage 2)
-option CONFIG_STACK_SIZE=0x10000
-option CONFIG_HEAP_SIZE=0x10000
-
-# Sandpoint Demo Board
-romimage "fallback"
-	## Base of ROM
-	option CONFIG_ROMBASE=0xfff00000
-
-	## Sandpoint reset vector
-	option CONFIG_RESET=CONFIG_ROMBASE+0x100
-
-	## Exception vectors (other than reset vector)
-	option CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100
-
-	## Start of coreboot in the boot rom
-	## = CONFIG_RESET + exeception vector table size
-	option CONFIG_ROMSTART=CONFIG_RESET+0x3100
-
-	## Coreboot C code runs at this location in RAM
-	option CONFIG_RAMBASE=0x00100000
-	option CONFIG_RAMSTART=0x00100000
-
-	option CONFIG_SANDPOINT_ALTIMUS=1
-
-	mainboard motorola/sandpoint
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"