From 6ccb252918c8a076dcf0a122e3aac028b4e80d4e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 13 Jun 2021 11:24:11 +0200 Subject: [PATCH] cpu/intel/msr.h: Sort MSRs in ascending order MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sort MSR definitions in ascending order to keep things organized. Change-Id: Iadfd28014dc6f41dae7b52b1550c699c89fe8bdc Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/55457 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- src/include/cpu/intel/msr.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h index 9d2b62f3d6..097ddb6e27 100644 --- a/src/include/cpu/intel/msr.h +++ b/src/include/cpu/intel/msr.h @@ -7,10 +7,6 @@ * Common MSRs for Intel CPUs */ -#define MSR_FEATURE_CONFIG 0x13c -#define AESNI_DISABLE (1 << 1) -#define AESNI_LOCK (1 << 0) - #define MSR_PIC_MSG_CONTROL 0x2e #define TPR_UPDATES_DISABLE (1 << 10) @@ -26,6 +22,10 @@ #define B_BOOT_GUARD_SACM_INFO_BTG_CAPABILITY (1ull << 32) #define B_BOOT_GUARD_SACM_INFO_TXT_CAPABILITY (1ull << 34) +#define MSR_FEATURE_CONFIG 0x13c +#define AESNI_DISABLE (1 << 1) +#define AESNI_LOCK (1 << 0) + #define MSR_PKG_C10_RESIDENCY 0x632 #endif /* CPU_INTEL_MSR_H */