sb/intel/bd82x6x: Do cosmetic fixes
Make the code follow the coding style, and reflow things that fit in 96 characters. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: I6e0acdc9c21d4b416597dc776bd9abab12bff4a0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -19,15 +19,13 @@
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#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
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static void
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wait_iobp(void)
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static void wait_iobp(void)
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{
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while (RCBA8(IOBPS) & 1)
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; // implement timeout?
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}
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static u32
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read_iobp(u32 address)
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static u32 read_iobp(u32 address)
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{
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u32 ret;
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@ -40,8 +38,7 @@ read_iobp(u32 address)
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return ret;
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}
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static void
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write_iobp(u32 address, u32 val)
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static void write_iobp(u32 address, u32 val)
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{
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/* this function was probably pch_iobp_update with the andvalue
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* being 0. So either the IOBP read can be removed or this function
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@ -137,11 +134,9 @@ void early_pch_init_native_dmi_post(void)
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;
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}
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void
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early_pch_init_native (void)
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void early_pch_init_native(void)
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{
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pci_write_config8 (SOUTHBRIDGE, 0xa6,
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pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2);
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pci_write_config8(SOUTHBRIDGE, 0xa6, pci_read_config8(SOUTHBRIDGE, 0xa6) | 2);
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RCBA32(CIR1) = 0x00109000;
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RCBA32(REC); // !!! = 0x00000000
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@ -278,9 +273,8 @@ static void pch_enable_lpc_decode(void)
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* - 0x3f8-0x3ff COMA
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*/
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pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
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pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
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| MC_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
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| COMB_LPC_EN | COMA_LPC_EN);
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pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN
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| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN);
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const struct device *dev = pcidev_on_root(0x1f, 0);
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const struct southbridge_intel_bd82x6x_config *config = NULL;
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@ -5,8 +5,7 @@
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include "pch.h"
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void
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southbridge_configure_default_intmap(void)
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void southbridge_configure_default_intmap(void)
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{
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/*
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* For the PCH internal PCI functions, provide a reasonable
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@ -83,8 +82,7 @@ southbridge_configure_default_intmap(void)
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(void) RCBA16(OIC);
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}
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void
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southbridge_rcba_config(void)
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void southbridge_rcba_config(void)
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{
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RCBA32(FD) = PCH_DISABLE_ALWAYS;
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}
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@ -36,34 +36,31 @@ void early_thermal_init(void)
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pci_write_config32(dev, 0x44, 0x0);
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/* Activate temporary BAR. */
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pci_write_config32(dev, 0x40,
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pci_read_config32(dev, 0x40) | 5);
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pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) | 5);
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write16p (0x40000004, 0x3a2b);
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write8p (0x4000000c, 0xff);
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write8p (0x4000000d, 0x00);
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write8p (0x4000000e, 0x40);
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write8p (0x40000082, 0x00);
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write8p (0x40000001, 0xba);
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write16p(0x40000004, 0x3a2b);
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write8p(0x4000000c, 0xff);
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write8p(0x4000000d, 0x00);
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write8p(0x4000000e, 0x40);
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write8p(0x40000082, 0x00);
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write8p(0x40000001, 0xba);
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/* Perform init. */
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/* Configure TJmax. */
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msr = rdmsr(MSR_TEMPERATURE_TARGET);
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write16p(0x40000012, ((msr.lo >> 16) & 0xff) << 6);
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/* Northbridge temperature slope and offset. */
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/* Northbridge temperature slope and offset */
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write16p(0x40000016, 0x808c);
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write16p (0x40000014, 0xde87);
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write16p(0x40000014, 0xde87);
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/* Enable thermal data reporting, processor, PCH and northbridge. */
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/* Enable thermal data reporting, processor, PCH and northbridge */
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write16p(0x4000001a, (read16p(0x4000001a) & ~0xf) | 0x10f0);
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/* Disable temporary BAR. */
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pci_write_config32(dev, 0x40,
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pci_read_config32(dev, 0x40) & ~1);
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/* Disable temporary BAR */
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pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) & ~1);
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pci_write_config32(dev, 0x40, 0);
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write32 (DEFAULT_RCBA + 0x38b0,
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(read32 (DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c);
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write32(DEFAULT_RCBA + 0x38b0, (read32(DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c);
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}
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