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sb/intel/bd82x6x: Do cosmetic fixes 

Make the code follow the coding style, and reflow things that fit in 96
characters.

Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.

Change-Id: I6e0acdc9c21d4b416597dc776bd9abab12bff4a0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Angel Pons 2020-05-07 00:54:42 +02:00 committed by Patrick Georgi
parent d8abb266f4
commit 6cd6e71b71
3 changed files with 22 additions and 33 deletions
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20
src/southbridge/intel/bd82x6x/early_pch.c
View File

@ -19,15 +19,13 @@
#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
static void static void wait_iobp(void)
wait_iobp(void)
{ {
while (RCBA8(IOBPS) & 1) while (RCBA8(IOBPS) & 1)
; // implement timeout? ; // implement timeout?
} }
static u32 static u32 read_iobp(u32 address)
read_iobp(u32 address)
{ {
u32 ret; u32 ret;
@ -40,8 +38,7 @@ read_iobp(u32 address)
return ret; return ret;
} }
static void static void write_iobp(u32 address, u32 val)
write_iobp(u32 address, u32 val)
{ {
/* this function was probably pch_iobp_update with the andvalue /* this function was probably pch_iobp_update with the andvalue
* being 0. So either the IOBP read can be removed or this function * being 0. So either the IOBP read can be removed or this function
@ -137,11 +134,9 @@ void early_pch_init_native_dmi_post(void)
; ;
} }
void void early_pch_init_native(void)
early_pch_init_native (void)
{ {
pci_write_config8 (SOUTHBRIDGE, 0xa6, pci_write_config8(SOUTHBRIDGE, 0xa6, pci_read_config8(SOUTHBRIDGE, 0xa6) | 2);
pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2);
RCBA32(CIR1) = 0x00109000; RCBA32(CIR1) = 0x00109000;
RCBA32(REC); // !!! = 0x00000000 RCBA32(REC); // !!! = 0x00000000
@ -278,9 +273,8 @@ static void pch_enable_lpc_decode(void)
* - 0x3f8-0x3ff COMA * - 0x3f8-0x3ff COMA
*/ */
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN
| MC_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN);
| COMB_LPC_EN | COMA_LPC_EN);
const struct device *dev = pcidev_on_root(0x1f, 0); const struct device *dev = pcidev_on_root(0x1f, 0);
const struct southbridge_intel_bd82x6x_config *config = NULL; const struct southbridge_intel_bd82x6x_config *config = NULL;

6
src/southbridge/intel/bd82x6x/early_rcba.c
View File

@ -5,8 +5,7 @@
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include "pch.h" #include "pch.h"
void void southbridge_configure_default_intmap(void)
southbridge_configure_default_intmap(void)
{ {
/* /*
* For the PCH internal PCI functions, provide a reasonable * For the PCH internal PCI functions, provide a reasonable
@ -83,8 +82,7 @@ southbridge_configure_default_intmap(void)
(void) RCBA16(OIC); (void) RCBA16(OIC);
} }
void void southbridge_rcba_config(void)
southbridge_rcba_config(void)
{ {
RCBA32(FD) = PCH_DISABLE_ALWAYS; RCBA32(FD) = PCH_DISABLE_ALWAYS;
} }

15
src/southbridge/intel/bd82x6x/early_thermal.c
View File

@ -36,8 +36,7 @@ void early_thermal_init(void)
pci_write_config32(dev, 0x44, 0x0); pci_write_config32(dev, 0x44, 0x0);
/* Activate temporary BAR. */ /* Activate temporary BAR. */
pci_write_config32(dev, 0x40, pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) | 5);
pci_read_config32(dev, 0x40) | 5);
write16p(0x40000004, 0x3a2b); write16p(0x40000004, 0x3a2b);
@ -51,19 +50,17 @@ void early_thermal_init(void)
/* Configure TJmax. */ /* Configure TJmax. */
msr = rdmsr(MSR_TEMPERATURE_TARGET); msr = rdmsr(MSR_TEMPERATURE_TARGET);
write16p(0x40000012, ((msr.lo >> 16) & 0xff) << 6); write16p(0x40000012, ((msr.lo >> 16) & 0xff) << 6);
/* Northbridge temperature slope and offset. */ /* Northbridge temperature slope and offset */
write16p(0x40000016, 0x808c); write16p(0x40000016, 0x808c);
write16p(0x40000014, 0xde87); write16p(0x40000014, 0xde87);
/* Enable thermal data reporting, processor, PCH and northbridge. */ /* Enable thermal data reporting, processor, PCH and northbridge */
write16p(0x4000001a, (read16p(0x4000001a) & ~0xf) | 0x10f0); write16p(0x4000001a, (read16p(0x4000001a) & ~0xf) | 0x10f0);
/* Disable temporary BAR. */ /* Disable temporary BAR */
pci_write_config32(dev, 0x40, pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) & ~1);
pci_read_config32(dev, 0x40) & ~1);
pci_write_config32(dev, 0x40, 0); pci_write_config32(dev, 0x40, 0);
write32 (DEFAULT_RCBA + 0x38b0, write32(DEFAULT_RCBA + 0x38b0, (read32(DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c);
(read32 (DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c);
} }