adding support for the Asus K8V-X
This pulls it all together and adds the real board-specific code. Confirmed to be working: - IDE - SATA - floppy - USB1.1 - USB2.0 - PS/2 keyboard - PS/2 mouse - serial - parport - sound - ethernet - PCI slots - AGP - powernow - fan speed monitoring - flashrom write Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/390 Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Tested-by: build bot (Jenkins)
This commit is contained in:
Florian Zumbiehl
Rudolf Marek
parent
f22a6d0c5e
commit
6cdf5a9e2e
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@ -27,6 +27,8 @@ config BOARD_ASUS_A8V_E_SE
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bool "A8V-E SE"
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config BOARD_ASUS_A8V_E_DELUXE
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bool "A8V-E Deluxe"
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config BOARD_ASUS_K8V_X
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bool "K8V-X"
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config BOARD_ASUS_M2N_E
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bool "M2N-E"
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config BOARD_ASUS_M2V
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@ -63,6 +65,7 @@ endchoice
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source "src/mainboard/asus/a8n_e/Kconfig"
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source "src/mainboard/asus/a8v-e_se/Kconfig"
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source "src/mainboard/asus/a8v-e_deluxe/Kconfig"
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source "src/mainboard/asus/k8v-x/Kconfig"
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source "src/mainboard/asus/m2n-e/Kconfig"
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source "src/mainboard/asus/m2v/Kconfig"
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source "src/mainboard/asus/m2v-mx_se/Kconfig"
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@ -1,26 +1,24 @@
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if BOARD_ASUS_A8V_E_SE
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if BOARD_ASUS_K8V_X
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select ARCH_X86
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select CPU_AMD_SOCKET_939
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select K8_HT_FREQ_1G_SUPPORT
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select CPU_AMD_SOCKET_754
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select NORTHBRIDGE_AMD_AMDK8
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select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
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select SOUTHBRIDGE_VIA_VT8237R
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select SOUTHBRIDGE_VIA_K8T890
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select SUPERIO_WINBOND_W83627EHG
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select SOUTHBRIDGE_VIA_K8T800_OLD
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select SUPERIO_WINBOND_W83697HF
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select HAVE_OPTION_TABLE
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select HAVE_ACPI_TABLES
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select HAVE_MP_TABLE
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select BOARD_ROMSIZE_KB_512
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select RAMINIT_SYSINFO
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select QRANK_DIMM_SUPPORT
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select SET_FIDVID
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config MAINBOARD_DIR
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string
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default asus/a8v-e_se
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default asus/k8v-x
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config DCACHE_RAM_BASE
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hex
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@ -44,7 +42,11 @@ config SB_HT_CHAIN_ON_BUS0
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config MAINBOARD_PART_NUMBER
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string
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default "A8V-E SE"
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default "K8V-X"
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config AGP_APERTURE_SIZE
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hex
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default 0x10000000
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config HW_MEM_HOLE_SIZEK
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hex
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@ -70,4 +72,4 @@ config HT_CHAIN_UNITID_BASE
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hex
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default 0x0
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endif # BOARD_ASUS_A8V_E_SE
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endif # BOARD_ASUS_K8V_X
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@ -30,7 +30,7 @@
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#include <device/device.h>
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#include <device/pci_ids.h>
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#include "southbridge/via/vt8237r/vt8237r.h"
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#include "southbridge/via/k8t890/k8t890.h"
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#include "southbridge/via/k8t890/k8x8xx.h"
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#include "northbridge/amd/amdk8/acpi.h"
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#include <cpu/amd/model_fxx_powernow.h>
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@ -1,6 +1,6 @@
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chip northbridge/amd/amdk8/root_complex # Root complex
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device lapic_cluster 0 on # APIC cluster
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chip cpu/amd/socket_939 # CPU
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chip cpu/amd/socket_754 # CPU
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device lapic 0 on end # APIC
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end
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end
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@ -16,8 +16,26 @@ chip northbridge/amd/amdk8/root_complex # Root complex
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register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
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register "fn_ctrl_lo" = "0" # Enable SB functions
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register "fn_ctrl_hi" = "0xad" # Enable SB functions
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register "usb2_termination_set" = "1"
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register "usb2_termination_a" = "8"
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register "usb2_termination_b" = "8"
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register "usb2_termination_c" = "6"
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register "usb2_termination_d" = "6"
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register "usb2_termination_e" = "6"
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register "usb2_termination_f" = "6"
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register "usb2_termination_g" = "6"
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register "usb2_termination_h" = "6"
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register "usb2_dpll_set" = "1"
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register "usb2_dpll_delay" = "3"
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register "int_efgh_as_gpio" = "1"
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register "enable_gpo3" = "1"
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register "disable_gpo26_gpo27" = "1"
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register "enable_aol_2_smb_slave" = "1"
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register "enable_gpo5" = "1"
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register "gpio15_12_dir_output" = "1"
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device pci 0.0 on end # HT
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device pci f.1 on end # IDE
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device pci 10.4 on end # USB2
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device pci 11.0 on # LPC
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chip drivers/generic/generic # DIMM 0-0-0
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device i2c 50 on end
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@ -28,10 +46,9 @@ chip northbridge/amd/amdk8/root_complex # Root complex
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chip drivers/generic/generic # DIMM 0-1-0
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device i2c 52 on end
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end
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chip drivers/generic/generic # DIMM 0-1-1
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device i2c 53 on end
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end
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chip superio/winbond/w83627ehg # Super I/O
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chip superio/winbond/w83697hf # Super I/O
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register "hwmon_fan1_divisor" = "128"
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register "hwmon_fan2_divisor" = "4"
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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@ -47,35 +64,19 @@ chip northbridge/amd/amdk8/root_complex # Root complex
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irq 0x70 = 4
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end
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device pnp 2e.3 off # Com2 (N/A on this board)
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 off # PS/2 keyboard & mouse (off)
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device pnp 2e.6 off # CIR
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end
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device pnp 2e.106 off # Serial flash interface (SFI)
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io 0x60 = 0x100
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device pnp 2e.7 off # Game port/GPIO 1
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end
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device pnp 2e.007 off # GPIO 1
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device pnp 2e.8 off # MIDI/GPIO 5
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end
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device pnp 2e.107 on # Game port
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io 0x60 = 0x201
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end
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device pnp 2e.207 on # MIDI
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io 0x62 = 0x330
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irq 0x70 = 0xa
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end
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device pnp 2e.307 off # GPIO 6
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end
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device pnp 2e.8 off # WDTO#, PLED
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end
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device pnp 2e.009 on # GPIO 2
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device pnp 2e.009 off # GPIO 2
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end
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device pnp 2e.109 off # GPIO 3
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end
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device pnp 2e.209 off # GPIO 4
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end
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device pnp 2e.309 on # GPIO 5
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end
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device pnp 2e.a off # ACPI
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end
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device pnp 2e.b on # Hardware monitor
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@ -84,6 +84,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1)
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/* PCI Routing Table */
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Name (_PRT, Package () {
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Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP slot, effectively */
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Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 },
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Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */
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Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
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Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },
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@ -96,88 +98,23 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1)
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Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },
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Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },
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Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },
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Package (0x04) { 0x000EFFFF, 0x00, 0x00, 0x13 }, /* Slot 0xE */
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Package (0x04) { 0x000EFFFF, 0x01, 0x00, 0x10 },
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Package (0x04) { 0x000EFFFF, 0x02, 0x00, 0x11 },
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Package (0x04) { 0x000EFFFF, 0x03, 0x00, 0x12 },
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Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x10 }, /* Slot 0x9 */
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Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x11 },
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Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x12 },
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Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x13 },
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Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x11 }, /* Marvell 88E8001 ethernet */
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Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */
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Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
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Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */
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Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
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Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
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Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
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Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */
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Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */
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Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
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Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
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Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
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Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */
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Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */
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Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */
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Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */
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Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 } /* AC97, MC97 */
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})
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Device (PEGG)
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{
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Name (_ADR, 0x00020000)
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Name (_UID, 0x00)
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Name (_BBN, 0x02)
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Name (_PRT, Package () {
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Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
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Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
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Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
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Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
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})
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}
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Device (PEX0)
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{
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Name (_ADR, 0x00030000)
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Name (_UID, 0x00)
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Name (_BBN, 0x03)
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Name (_PRT, Package () {
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Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
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Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
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Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
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Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
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})
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}
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Device (PEX1)
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{
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Name (_ADR, 0x00030001)
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Name (_UID, 0x00)
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Name (_BBN, 0x04)
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Name (_PRT, Package () {
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Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
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Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
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Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
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Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
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})
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}
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Device (PEX2)
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{
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Name (_ADR, 0x00030002)
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Name (_UID, 0x00)
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Name (_BBN, 0x05)
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Name (_PRT, Package () {
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Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
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Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
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Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
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Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
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})
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}
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Device (PEX3)
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{
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Name (_ADR, 0x00030003)
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Name (_UID, 0x00)
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Name (_BBN, 0x06)
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Name (_PRT, Package () {
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Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */
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Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 },
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Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A },
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Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B },
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})
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}
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Device (ISA) {
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Name (_ADR, 0x00110000)
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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* Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -21,8 +22,43 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include "southbridge/via/vt8237r/vt8237r.h"
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#include "chip.h"
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u32 vt8237_ide_80pin_detect(struct device *dev)
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{
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device_t lpc_dev;
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u16 acpi_io_base;
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u32 gpio_in;
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u32 res;
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lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
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if (!lpc_dev)
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return 0;
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acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1;
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if (!acpi_io_base)
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return 0;
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/* select function GPIO29 for pin AB9 */
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pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08);
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gpio_in = inl(acpi_io_base + 0x48);
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/* bit 29 for primary port, clear if unconnected or 80-pin cable */
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res = gpio_in & (1<<29) ? 0 : VT8237R_IDE0_80PIN_CABLE;
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/* bit 8 for secondary port, clear if unconnected or 80-pin cable */
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res |= gpio_in & (1<<8) ? 0 : VT8237R_IDE1_80PIN_CABLE;
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printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary",
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res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40);
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printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary",
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res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40);
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return res;
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}
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struct chip_operations mainboard_ops = {
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CHIP_NAME("ASUS A8V-E SE Mainboard")
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CHIP_NAME("ASUS K8V-X Mainboard")
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};
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@ -22,7 +22,7 @@
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#include <arch/smp/mpspec.h>
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#include <arch/ioapic.h>
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#include "southbridge/via/vt8237r/vt8237r.h"
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#include "southbridge/via/k8t890/k8t890.h"
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#include "southbridge/via/k8t890/k8x8xx.h"
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static void *smp_write_config_table(void *v)
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{
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@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus);
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#include "superio/winbond/w83627ehg/early_serial.c"
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#include "superio/winbond/w83697hf/early_serial.c"
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#include "southbridge/via/vt8237r/early_smbus.c"
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#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
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#include "cpu/x86/mtrr/earlymtrr.c"
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@ -48,9 +48,7 @@ unsigned int get_sbdn(unsigned bus);
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#include "northbridge/amd/amdk8/setup_resource_map.c"
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#include <spd.h>
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#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
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#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V)
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#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
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#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
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static void memreset(int controllers, const struct mem_controller *ctrl) { }
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static void activate_spd_rom(const struct mem_controller *ctrl) { }
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||||
|
|
@ -105,52 +103,25 @@ static void sio_init(void)
|
|||
u8 reg;
|
||||
|
||||
pnp_enter_ext_func_mode(SERIAL_DEV);
|
||||
/* We have 24MHz input. */
|
||||
reg = pnp_read_config(SERIAL_DEV, 0x24);
|
||||
pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
|
||||
/* We have GPIO for KB/MS pin. */
|
||||
reg = pnp_read_config(SERIAL_DEV, 0x2a);
|
||||
pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1));
|
||||
/* We have all RESTOUT and even some reserved bits, too. */
|
||||
reg = pnp_read_config(SERIAL_DEV, 0x2c);
|
||||
pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
|
||||
pnp_exit_ext_func_mode(SERIAL_DEV);
|
||||
|
||||
pnp_enter_ext_func_mode(ACPI_DEV);
|
||||
pnp_set_logical_device(ACPI_DEV);
|
||||
/*
|
||||
* Set the delay rising time from PWROK_LP to PWROK_ST to
|
||||
* 300 - 600ms, and 0 to vice versa.
|
||||
*/
|
||||
reg = pnp_read_config(ACPI_DEV, 0xe6);
|
||||
pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0));
|
||||
/* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
|
||||
reg = pnp_read_config(ACPI_DEV, 0xe4);
|
||||
pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
|
||||
pnp_exit_ext_func_mode(ACPI_DEV);
|
||||
|
||||
pnp_enter_ext_func_mode(GPIO_DEV);
|
||||
pnp_set_logical_device(GPIO_DEV);
|
||||
/* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
|
||||
pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */
|
||||
pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */
|
||||
pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */
|
||||
pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */
|
||||
pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */
|
||||
pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */
|
||||
pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */
|
||||
pnp_exit_ext_func_mode(GPIO_DEV);
|
||||
/* 4 Mbit flash */
|
||||
reg = (reg & ~0x30) | 0x20;
|
||||
/* We have 24MHz input. */
|
||||
reg &= ~0x40;
|
||||
/* enable MEMW#, so flash can be written */
|
||||
reg |= 0x08;
|
||||
pnp_write_config(SERIAL_DEV, 0x24, reg);
|
||||
}
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
static const uint16_t spd_addr[] = {
|
||||
// Node 0
|
||||
DIMM0, DIMM2, 0, 0,
|
||||
DIMM1, DIMM3, 0, 0,
|
||||
DIMM0, DIMM1, DIMM2, 0,
|
||||
0, 0, 0, 0,
|
||||
// Node 1
|
||||
DIMM4, DIMM6, 0, 0,
|
||||
DIMM5, DIMM7, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
};
|
||||
unsigned bsp_apicid = 0;
|
||||
int needs_reset = 0;
|
||||
|
|
@ -158,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
|
||||
|
||||
sio_init();
|
||||
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
enable_rom_decode();
|
||||
|
||||
|
|
@ -173,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
|
||||
// FIXME why is this executed again? --->
|
||||
sio_init();
|
||||
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
enable_rom_decode();
|
||||
// <--- FIXME why is this executed again?
|
||||
|
|
@ -209,7 +180,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
soft_reset();
|
||||
}
|
||||
|
||||
/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
|
||||
/* the HT settings needs to be OK, because link freq change may cause HT disconnect */
|
||||
vt8237_sb_enable_fid_vid();
|
||||
enable_fid_change();
|
||||
init_fidvid_bsp(bsp_apicid);
|
||||
|
||||
|
|
@ -220,6 +192,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
|
||||
enable_smbus();
|
||||
|
||||
/* this seems to be some GPIO on the SMBus--in any case, setting these
|
||||
* two bits reduces the pullup impedance of the bus lines and is required
|
||||
* in order to be able to read SPD info */
|
||||
smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80);
|
||||
smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10);
|
||||
|
||||
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
|
||||
post_cache_as_ram();
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue