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soc/intel/baytrail: Use a variable for s3resume 

This helps towards unified chipset_power_state.

Change-Id: I532384ad6c5b2e793ed70f31763f2c8873443816
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2021-02-17 20:43:04 +02:00
parent cdb5b56303
commit 6ceec167f5
1 changed files with 4 additions and 2 deletions
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6
src/soc/intel/baytrail/romstage/romstage.c
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@ -108,12 +108,14 @@ void mainboard_romstage_entry(void)
printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state); printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state);
elog_boot_notify(prev_sleep_state == ACPI_S3); int s3resume = prev_sleep_state == ACPI_S3;
elog_boot_notify(s3resume);
/* Initialize RAM */ /* Initialize RAM */
raminit(&mp, prev_sleep_state); raminit(&mp, prev_sleep_state);
timestamp_add_now(TS_AFTER_INITRAM); timestamp_add_now(TS_AFTER_INITRAM);
romstage_handoff_init(prev_sleep_state == ACPI_S3); romstage_handoff_init(s3resume);
} }