soc/intel/cannonlake: Add finalize function
Before OS boot up, the following actions need to be taken. 1. Lock down PMC/SPI/DMI/TCO register. 2. Disable Sideband Access. 3. Disable Heci interface. 4. Disable PMtimer base on config settings. TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp board. Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21943 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lijian Zhao
Aaron Durbin
parent
53660ed499
commit
6cf501c3ae
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@ -30,6 +30,7 @@ romstage-$(CONFIG_UART_DEBUG) += uart.c
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ramstage-y += acpi.c
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ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += finalize.c
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ramstage-y += gpio.c
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ramstage-y += gspi.c
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ramstage-y += gpio.c
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@ -0,0 +1,146 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <bootstate.h>
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#include <chip.h>
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#include <console/console.h>
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#include <console/post_codes.h>
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#include <cpu/x86/smm.h>
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#include <device/pci.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <reg_script.h>
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#include <spi-generic.h>
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#include <soc/p2sb.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include <soc/smbus.h>
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#include <soc/systemagent.h>
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#include <stdlib.h>
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#define PSF_BASE_ADDRESS 0x300
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#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
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#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8)
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static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask)
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{
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uint32_t reg32;
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reg32 = pci_read_config32(dev, PCH_P2SB_EPMASK(epmask_id));
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pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask);
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}
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static void disable_sideband_access(void)
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{
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device_t dev;
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u8 reg8;
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uint32_t mask;
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dev = PCH_DEV_P2SB;
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/* Remove the host accessing right to PSF register range. */
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/* Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to [1, 1, 1, 1] */
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mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26);
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pch_configure_endpoints(dev, 5, mask);
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/* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */
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reg8 = pci_read_config8(dev, PCH_P2SB_E0 + 2);
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pci_write_config8(dev, PCH_P2SB_E0 + 2, reg8 | (1 << 1));
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}
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static void pch_disable_heci(void)
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{
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device_t dev = PCH_DEV_P2SB;
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/*
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* if p2sb device 1f.1 is not present or hidden in devicetree
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* p2sb device becomes NULL
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*/
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if (!dev)
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return;
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/* unhide p2sb device */
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pci_write_config8(dev, PCH_P2SB_E0 + 1, 0);
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/* disable heci#1 */
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pcr_or32(PID_PSF1, PSF_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN,
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PCR_PSFX_T0_SHDW_PCIEN_FUNDIS);
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disable_sideband_access();
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/* hide p2sb device */
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pci_write_config8(dev, PCH_P2SB_E0 + 1, 1);
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}
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static void pch_finalize(void)
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{
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device_t dev;
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uint32_t reg32;
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uint16_t tcobase, tcocnt;
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uint8_t *pmcbase;
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config_t *config;
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uint8_t reg8;
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/* TCO Lock down */
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tcobase = smbus_tco_regs();
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tcocnt = inw(tcobase + TCO1_CNT);
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tcocnt |= TCO_LOCK;
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outw(tcocnt, tcobase + TCO1_CNT);
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/*
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* Disable ACPI PM timer based on dt policy
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*
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* Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
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* Disabling ACPI PM timer also switches off TCO
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*/
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dev = PCH_DEV_PMC;
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config = dev->chip_info;
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pmcbase = pmc_mmio_regs();
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if (config->PmTimerDisabled) {
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reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);
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reg8 |= (1 << 1);
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write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
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}
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/* Disable XTAL shutdown qualification for low power idle. */
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if (config->s0ix_enable) {
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reg32 = read32(pmcbase + CPPMVRIC);
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reg32 |= XTALSDQDIS;
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write32(pmcbase + CPPMVRIC, reg32);
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}
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/* we should disable Heci1 based on the devicetree policy */
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if (config->HeciEnabled == 0)
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pch_disable_heci();
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}
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static void soc_finalize(void *unused)
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{
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printk(BIOS_DEBUG, "Finalizing chipset.\n");
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pch_finalize();
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printk(BIOS_DEBUG, "Finalizing SMM.\n");
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outb(APM_CNT_FINALIZE, APM_CNT);
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/* Indicate finalize step with post code */
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post_code(POST_OS_BOOT);
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}
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BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);
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@ -120,6 +120,9 @@
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#define GBLRST_CAUSE0_THERMTRIP (1 << 5)
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#define GBLRST_CAUSE1 0x1928
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#define CPPMVRIC 0x1B1C
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#define XTALSDQDIS (1 << 22)
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#define IRQ_REG ACTL
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#define SCI_IRQ_ADJUST 0
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#define ACTL 0x1BD8
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@ -0,0 +1,113 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <bootstate.h>
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#include <chip.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include <string.h>
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#define PCR_DMI_GCS 0x274C
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#define PCR_DMI_GCS_BILD (1 << 0)
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static void pmc_lockdown_cfg(const struct soc_intel_cannonlake_config *config)
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{
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uint8_t *pmcbase;
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uint32_t reg32, pmsyncreg;
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/* PMSYNC */
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pmcbase = pmc_mmio_regs();
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pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
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pmsyncreg |= PMSYNC_LOCK;
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write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
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/* Lock down ABASE and sleep stretching policy */
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reg32 = read32(pmcbase + GEN_PMCON_B);
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reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
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write32(pmcbase + GEN_PMCON_B, reg32);
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if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
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pmcbase = pmc_mmio_regs();
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reg8 = read8(pmcbase + GEN_PMCON_B);
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reg8 |= SMI_LOCK;
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write8(pmcbase + GEN_PMCON_B, reg8);
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}
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}
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static void dmi_lockdown_cfg(void)
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{
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/*
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* GCS reg of DMI
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*
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* When set, prevents GCS.BBS from being changed
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* GCS.BBS: (Boot BIOS Strap) This field determines the destination
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* of accesses to the BIOS memory range.
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* Bits Description
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* “0b”: SPI
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* “1b”: LPC/eSPI
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*/
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pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
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}
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static void spi_lockdown_cfg(const struct soc_intel_cannonlake_config *config)
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{
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/* Set FAST_SPI opcode menu */
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fast_spi_set_opcode_menu();
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/* Discrete Lock Flash PR registers */
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fast_spi_pr_dlock();
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/* Lock FAST_SPIBAR */
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fast_spi_lock_bar();
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/* Set Bios Interface Lock, Bios Lock */
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if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
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/* Bios Interface Lock */
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fast_spi_set_bios_interface_lock_down();
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/* Bios Lock */
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fast_spi_set_lock_enable();
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}
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}
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static void platform_lockdown_config(void *unused)
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{
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struct soc_intel_cannonlake_config *config;
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struct device *dev;
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dev = PCH_DEV_SPI;
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/* Check if device is valid, else return */
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if (dev == NULL || dev->chip_info == NULL)
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return;
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config = dev->chip_info;
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/* SPI lock down configuration */
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spi_lockdown_cfg(config);
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/* DMI lock down configuration */
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dmi_lockdown_cfg();
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/* PMC lock down configuration */
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pmc_lockdown_cfg(config);
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config,
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NULL);
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