mb/google/brya/var/agah: Disable thunderbolt interface
Agah doesn't support TBT interface so disable it in devicetree, for fitimage configuration is at chrome-internal:4846869. BUG=b:224423318 TEST=Build and check DUT boots. Change-Id: I1eb43e86de5debf24ebde6eace14fe04bad5e5b1 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65699 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
parent
e3ed9cacaa
commit
6cfe2624a2
|
@ -59,6 +59,12 @@ chip soc/intel/alderlake
|
||||||
}"
|
}"
|
||||||
|
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
|
device ref tbt_pcie_rp0 off end
|
||||||
|
device ref tbt_pcie_rp1 off end
|
||||||
|
device ref tbt_pcie_rp2 off end
|
||||||
|
|
||||||
|
device ref tcss_dma0 off end
|
||||||
|
device ref tcss_dma1 off end
|
||||||
device ref pcie4_0 on
|
device ref pcie4_0 on
|
||||||
# Enable CPU PCIe RP 1 using CLKREQ 0 and CLKSRC 0
|
# Enable CPU PCIe RP 1 using CLKREQ 0 and CLKSRC 0
|
||||||
register "cpu_pcie_rp[CPU_RP(1)]" = "{
|
register "cpu_pcie_rp[CPU_RP(1)]" = "{
|
||||||
|
|
Loading…
Reference in New Issue