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haswell: always use MMIO PCI config accesses 

Add a bootblock.c file for the northbridge and setup the
PCIEXBAR as the first thing using IO PCI config acceses.
After that all PCI config accesses can use MMIO.

Change-Id: I51d229c626c45705dda1757c2f14265cbc0e6183
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2617
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Aaron Durbin 2012-10-31 22:57:16 -05:00 committed by Ronald G. Minnich
parent 76c3700f02
commit 6d04f0f89e
3 changed files with 32 additions and 3 deletions
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5
src/northbridge/intel/haswell/Kconfig
View File

@ -22,9 +22,14 @@ config NORTHBRIDGE_INTEL_HASWELL
select CACHE_MRC_BIN
select CPU_INTEL_HASWELL
select REQUIRES_BLOB
select MMCONF_SUPPORT_DEFAULT
if NORTHBRIDGE_INTEL_HASWELL
config BOOTBLOCK_NORTHBRIDGE_INIT
string
default "northbridge/intel/haswell/bootblock.c"
config VGA_BIOS_ID
string
default "8086,0166"

27
src/northbridge/intel/haswell/bootblock.c Normal file
View File

@ -0,0 +1,27 @@
#include <arch/io.h>
#include <arch/romcc_io.h>
/* Just re-define this instead of including haswell.h. It blows up romcc. */
#define PCIEXBAR 0x60
static void bootblock_northbridge_init(void)
{
uint32_t reg;
/*
* The "io" variant of the config access is explicitly used to
* setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
* to true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
* CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
*/
reg = 0;
pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg);
reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg);
}

3
src/northbridge/intel/haswell/early_init.c
View File

@ -26,7 +26,6 @@
#include <device/pci_def.h>
#include <elog.h>
#include "haswell.h"
#include "pcie_config.c"
static void haswell_setup_bars(void)
{
@ -50,8 +49,6 @@ static void haswell_setup_bars(void)
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32);
pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32);
pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */
pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR + 4, (0LL+DEFAULT_PCIEXBAR) >> 32);
pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+DEFAULT_DMIBAR) >> 32);