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Fix eagleheights 

not a 6ex board, but using the same CAR code.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5414 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-04-13 00:02:20 +00:00 committed by Stefan Reinauer
parent 1977b891c5
commit 6d1b0d84f2
1 changed files with 1 additions and 4 deletions
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5
src/mainboard/intel/eagleheights/romstage.c
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@ -163,7 +163,7 @@ void early_config(void) {
pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0));
}
void real_main(unsigned long bist)
void main(unsigned long bist)
{
/* int boot_mode = 0; */
@ -232,6 +232,3 @@ void real_main(unsigned long bist)
sdram_initialize(ARRAY_SIZE(mch), mch);
}
/* Use Intel Core (not Core 2) code for CAR init, any CPU might be used. */
#include "cpu/intel/model_6ex/cache_as_ram_disable.c"