diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h
index 00210a7fe1..11acc78228 100644
--- a/src/soc/amd/common/block/include/amdblocks/lpc.h
+++ b/src/soc/amd/common/block/include/amdblocks/lpc.h
@@ -180,6 +180,15 @@ int lpc_set_wideio_range(uint16_t start, uint16_t size);
 
 uintptr_t lpc_get_spibase(void);
 
+/*
+ * Perform early initialization for LPC:
+ * 1. Enable LPC controller
+ * 2. Disable any LPC decodes
+ * 3. Set SPI Base which is the MMIO base for both SPI and eSPI controller (if supported by
+ * platform).
+ */
+void lpc_early_init(void);
+
 /*
  * Sets MMIO base address for SPI controller and eSPI controller (if supported by platform).
  *
diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c
index 2c47a8549a..d2a65c8c96 100644
--- a/src/soc/amd/common/block/lpc/lpc_util.c
+++ b/src/soc/amd/common/block/lpc/lpc_util.c
@@ -5,6 +5,7 @@
 #include <device/device.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
+#include <amdblocks/acpimmio.h>
 #include <amdblocks/lpc.h>
 #include <soc/iomap.h>
 #include <soc/southbridge.h>
@@ -349,3 +350,20 @@ void lpc_enable_spi_rom(uint32_t enable)
 
 	pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, reg32);
 }
+
+static void lpc_enable_controller(void)
+{
+	u8 byte;
+
+	/* Enable LPC controller */
+	byte = pm_io_read8(PM_LPC_GATING);
+	byte |= PM_LPC_ENABLE;
+	pm_io_write8(PM_LPC_GATING, byte);
+}
+
+void lpc_early_init(void)
+{
+	lpc_enable_controller();
+	lpc_disable_decodes();
+	lpc_set_spibase(SPI_BASE_ADDRESS);
+}