tegra210: Increase size of verstage due to overflow

When imlpementing changes in VBOOT, within the build process, tegra210
overflows into the romstage. Reduce the size of romstage from 104 to
100 and increase the size from verstage from 66 to 70.

Change-Id: Ie00498838a644a6f92881db85833dd0a94b87f53
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34640
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Christian Walter 2019-07-31 16:23:53 +02:00 committed by Philipp Deppenwiese
parent 9c0fe34511
commit 6d2dbe11ae
1 changed files with 8 additions and 8 deletions

View File

@ -29,17 +29,17 @@ SECTIONS
{
SRAM_START(0x40000000)
PRERAM_CBMEM_CONSOLE(0x40000000, 2K)
PRERAM_CBFS_CACHE(0x40000800, 32K)
VBOOT2_WORK(0x40008800, 12K)
VBOOT2_TPM_LOG(0x4000B800, 2K)
PRERAM_CBFS_CACHE(0x40000800, 30K)
VBOOT2_WORK(0x40008000, 12K)
VBOOT2_TPM_LOG(0x4000B000, 2K)
#if ENV_ARM64
STACK(0x4000C000, 3K)
STACK(0x4000B800, 3K)
#else /* AVP gets a separate stack to avoid any chance of handoff races. */
STACK(0x4000CC00, 3K)
STACK(0x4000C400, 3K)
#endif
TIMESTAMP(0x4000D800, 2K)
BOOTBLOCK(0x4000E000, 30K)
VERSTAGE(0x40015800, 66K)
TIMESTAMP(0x4000D000, 2K)
BOOTBLOCK(0x4000D800, 30K)
VERSTAGE(0x40015000, 68k)
ROMSTAGE(0x40026000, 104K)
SRAM_END(0x40040000)