mb/lenovo/g505s: Format code

Change-Id: I9cce00e1634d62a63b3563d54a7a0c56058d0e39
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Elyes Haouas 2022-02-14 09:27:48 +01:00 committed by Felix Held
parent 8f38e5f5dc
commit 6d508dfc2d
3 changed files with 7 additions and 10 deletions

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@ -182,15 +182,14 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
* data from the table. Otherwise, it will use its default conservative settings * data from the table. Otherwise, it will use its default conservative settings
*/ */
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), PSO_END
NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
PSO_END
}; };
void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)

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@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* AcpiGpe0Blk */ /* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
Field(GP0B, ByteAcc, NoLock, Preserve) { Field(GP0B, ByteAcc, NoLock, Preserve) {

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@ -26,7 +26,6 @@ static const u8 mainboard_intr_data[0x54] = {
0x10, 0x11, 0x12, 0x13 0x10, 0x11, 0x12, 0x13
}; };
static void pavilion_cold_boot_init(void) static void pavilion_cold_boot_init(void)
{ {
/* Lid SMI is only used in non-ACPI mode; leave it off in S3 resume */ /* Lid SMI is only used in non-ACPI mode; leave it off in S3 resume */