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hp/pavilion_m6_1035dx: Enable IOMMU 

Change-Id: Ia14490c9074d35b7dde99e38b4ee169d4e4589a4
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7678
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Alexandru Gagniuc 2014-12-06 03:29:25 -06:00
parent afe6a69b33
commit 6d5657d620
4 changed files with 13 additions and 1 deletions
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5
src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl
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@ -22,6 +22,11 @@
Name(PR0, Package(){
/* NB devices */
/* Bus 0, Dev 0 - F15 Host Controller */
Package(){0x0000FFFF, 0, INTA, 0 },
Package(){0x0000FFFF, 1, INTB, 0 },
Package(){0x0000FFFF, 2, INTC, 0 },
Package(){0x0000FFFF, 3, INTD, 0 },
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
Package(){0x0001FFFF, 0, INTB, 0 },
Package(){0x0001FFFF, 1, INTC, 0 },

2
src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
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@ -186,7 +186,7 @@
#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
#endif
#define BLDCFG_IOMMU_SUPPORT FALSE
#define BLDCFG_IOMMU_SUPPORT TRUE
#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID

1
src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb
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@ -30,6 +30,7 @@ chip northbridge/amd/agesa/family15tn/root_complex
chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 0.2 on end # IOMMU
device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
device pci 1.1 on end # Internal Multimedia
device pci 3.0 off end

6
src/mainboard/hp/pavilion_m6_1035dx/mptable.c
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@ -118,6 +118,12 @@ static void *smp_write_config_table(void *v)
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* IOMMU */
PCI_INT(0x0, 0x00, 0x0, 0x10);
PCI_INT(0x0, 0x00, 0x1, 0x11);
PCI_INT(0x0, 0x00, 0x2, 0x12);
PCI_INT(0x0, 0x00, 0x3, 0x13);
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);