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soc/intel/meteorlake: provide a list of D-states to enter LPM 

Provide D-states to enter LPM (S0ix) for MTL

Values were copied over from corresponding ADL file (as MTL data
sheet is not yet available).

TEST=Built and tested on Rex by verifying SSDT contents

Change-Id: If367511a29726669fe25ad2124e2f9b877a31ee8
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
This commit is contained in:
Eran Mitrani 2023-01-03 14:29:35 -08:00 committed by Felix Held
parent d83cd8bd85
commit 6d5d59648a
1 changed files with 59 additions and 0 deletions
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59
src/soc/intel/meteorlake/acpi.c
View File

@ -167,6 +167,65 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
}
static struct min_sleep_state min_pci_sleep_states[] = {
{ SA_DEVFN_ROOT, ACPI_DEVICE_SLEEP_D3 },
{ SA_DEVFN_IGD, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_DPTF, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_IPU, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_TBT0, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_TBT1, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_TBT2, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_TBT3, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_GNA, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_TCSS_XHCI, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_TCSS_XDCI, ACPI_DEVICE_SLEEP_D3 },
{ SA_DEVFN_TCSS_DMA0, ACPI_DEVICE_SLEEP_D3 },
{ SA_DEVFN_TCSS_DMA1, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_VMD, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_THC0, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_THC1, ACPI_DEVICE_SLEEP_D3 },
{ PCH_DEVFN_XHCI, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_USBOTG, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_SRAM, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_CNVI_WIFI, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_I2C0, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_I2C1, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_I2C2, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_I2C3, ACPI_DEVICE_SLEEP_D3 },
{ PCH_DEVFN_CSE, ACPI_DEVICE_SLEEP_D0 },
{ PCI_DEVFN_SATA, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_I2C4, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_I2C5, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_UART2, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_PCIE1, ACPI_DEVICE_SLEEP_D0 },
{ PCI_DEVFN_PCIE2, ACPI_DEVICE_SLEEP_D0 },
{ PCI_DEVFN_PCIE3, ACPI_DEVICE_SLEEP_D0 },
{ PCI_DEVFN_PCIE4, ACPI_DEVICE_SLEEP_D0 },
{ PCI_DEVFN_PCIE5, ACPI_DEVICE_SLEEP_D0 },
{ PCI_DEVFN_PCIE6, ACPI_DEVICE_SLEEP_D0 },
{ PCI_DEVFN_PCIE7, ACPI_DEVICE_SLEEP_D0 },
{ PCI_DEVFN_PCIE8, ACPI_DEVICE_SLEEP_D0 },
{ PCI_DEVFN_PCIE9, ACPI_DEVICE_SLEEP_D0 },
{ PCI_DEVFN_PCIE10, ACPI_DEVICE_SLEEP_D0 },
{ PCI_DEVFN_PCIE11, ACPI_DEVICE_SLEEP_D0 },
{ PCI_DEVFN_PCIE12, ACPI_DEVICE_SLEEP_D0 },
{ PCI_DEVFN_UART0, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_UART1, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_GSPI0, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_GSPI1, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_ESPI, ACPI_DEVICE_SLEEP_D0 },
{ PCH_DEVFN_PMC, ACPI_DEVICE_SLEEP_D0 },
{ PCI_DEVFN_HDA, ACPI_DEVICE_SLEEP_D0 },
{ PCI_DEVFN_SPI, ACPI_DEVICE_SLEEP_D3 },
{ PCI_DEVFN_GBE, ACPI_DEVICE_SLEEP_D3 },
};
struct min_sleep_state *soc_get_min_sleep_state_array(size_t *size)
{
*size = ARRAY_SIZE(min_pci_sleep_states);
return min_pci_sleep_states;
}
uint32_t soc_read_sci_irq_select(void)
{
return read32p(soc_read_pmc_base() + IRQ_REG);