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soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array 

This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ#
from mainboards instead of defining a separate property for each root
port. This allows us to use memcpy to copy the entire array into FSP
params as well as new properties for PCIe root ports can be added as
arrays in future CLs.

BUG=b:74633273
BRANCH=reef,coral

Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2018-03-14 19:57:16 -07:00
parent 211bb97c67
commit 6d5e10c05d
12 changed files with 64 additions and 72 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/mainboard/google/reef/variants/baseboard/devicetree.cb
View File

@ -4,13 +4,13 @@ chip soc/intel/apollolake
device lapic 0 on end device lapic 0 on end
end end
register "pcie_rp0_clkreq_pin" = "0" # wifi/bt register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
# Disable unused clkreq of PCIe root ports # Disable unused clkreq of PCIe root ports
register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0 # GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO # If the Board has PERST_0 signal, assign the GPIO

12
src/mainboard/google/reef/variants/coral/devicetree.cb
View File

@ -4,13 +4,13 @@ chip soc/intel/apollolake
device lapic 0 on end device lapic 0 on end
end end
register "pcie_rp0_clkreq_pin" = "0" # wifi/bt register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
# Disable unused clkreq of PCIe root ports # Disable unused clkreq of PCIe root ports
register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0 # GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO # If the Board has PERST_0 signal, assign the GPIO

12
src/mainboard/google/reef/variants/pyro/devicetree.cb
View File

@ -4,13 +4,13 @@ chip soc/intel/apollolake
device lapic 0 on end device lapic 0 on end
end end
register "pcie_rp0_clkreq_pin" = "0" # wifi/bt register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
# Disable unused clkreq of PCIe root ports # Disable unused clkreq of PCIe root ports
register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0 # GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO # If the Board has PERST_0 signal, assign the GPIO

12
src/mainboard/google/reef/variants/sand/devicetree.cb
View File

@ -4,13 +4,13 @@ chip soc/intel/apollolake
device lapic 0 on end device lapic 0 on end
end end
register "pcie_rp0_clkreq_pin" = "0" # wifi/bt register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
# Disable unused clkreq of PCIe root ports # Disable unused clkreq of PCIe root ports
register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0 # GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO # If the Board has PERST_0 signal, assign the GPIO

12
src/mainboard/google/reef/variants/snappy/devicetree.cb
View File

@ -4,13 +4,13 @@ chip soc/intel/apollolake
device lapic 0 on end device lapic 0 on end
end end
register "pcie_rp0_clkreq_pin" = "0" # wifi/bt register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
# Disable unused clkreq of PCIe root ports # Disable unused clkreq of PCIe root ports
register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0 # GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO # If the Board has PERST_0 signal, assign the GPIO

12
src/mainboard/intel/apollolake_rvp/devicetree.cb
View File

@ -1,11 +1,11 @@
chip soc/intel/apollolake chip soc/intel/apollolake
register "pcie_rp0_clkreq_pin" = "2" # PCIe slot 2 register "pcie_rp_clkreq_pin[0]" = "2" # PCIe slot 2
register "pcie_rp1_clkreq_pin" = "3" # Wifi+BT M2 slot register "pcie_rp_clkreq_pin[1]" = "3" # Wifi+BT M2 slot
register "pcie_rp2_clkreq_pin" = "0" # PCIe slot 1 register "pcie_rp_clkreq_pin[2]" = "0" # PCIe slot 1
register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
device cpu_cluster 0 on device cpu_cluster 0 on
device lapic 0 on end device lapic 0 on end

12
src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
View File

@ -4,13 +4,13 @@ chip soc/intel/apollolake
device lapic 0 on end device lapic 0 on end
end end
register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
# Disable unused clkreq of PCIe root ports # Disable unused clkreq of PCIe root ports
register "pcie_rp1_clkreq_pin" = "3" # wifi/bt register "pcie_rp_clkreq_pin[1]" = "3" # wifi/bt
register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
register "pcie_rp4_clkreq_pin" = "1" register "pcie_rp_clkreq_pin[4]" = "1"
register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0 # GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO # If the Board has PERST_0 signal, assign the GPIO

12
src/mainboard/intel/leafhill/devicetree.cb
View File

@ -1,11 +1,11 @@
chip soc/intel/apollolake chip soc/intel/apollolake
register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
device cpu_cluster 0 on device cpu_cluster 0 on
device lapic 0 on end device lapic 0 on end

12
src/mainboard/intel/minnow3/devicetree.cb
View File

@ -1,11 +1,11 @@
chip soc/intel/apollolake chip soc/intel/apollolake
register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
device cpu_cluster 0 on device cpu_cluster 0 on
device lapic 0 on end device lapic 0 on end

12
src/mainboard/siemens/mc_apl1/devicetree.cb
View File

@ -7,12 +7,12 @@ chip soc/intel/apollolake
register "sci_irq" = "SCIS_IRQ10" register "sci_irq" = "SCIS_IRQ10"
# Disable unused clkreq of PCIe root ports # Disable unused clkreq of PCIe root ports
register "pcie_rp0_clkreq_pin" = "3" # PCIe-PCI-Bridge register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge
register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
register "pcie_rp2_clkreq_pin" = "0" # MACPHY register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY
register "pcie_rp3_clkreq_pin" = "1" # MACPHY register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY
register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# EMMC TX DATA Delay 1 # EMMC TX DATA Delay 1
# Refer to EDS-Vol2-22.3. # Refer to EDS-Vol2-22.3.

8
src/soc/intel/apollolake/chip.c
View File

@ -531,12 +531,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
/* Parse device tree and disable unused device*/ /* Parse device tree and disable unused device*/
parse_devicetree(silconfig); parse_devicetree(silconfig);
silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin; memcpy(silconfig->PcieRpClkReqNumber, cfg->pcie_rp_clkreq_pin,
silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin; sizeof(silconfig->PcieRpClkReqNumber));
silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin;
silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin;
silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin;
silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin;
if (cfg->emmc_tx_cmd_cntl != 0) if (cfg->emmc_tx_cmd_cntl != 0)
silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl; silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl;

8
src/soc/intel/apollolake/chip.h
View File

@ -28,6 +28,7 @@
#include <soc/pm.h> #include <soc/pm.h>
#include <soc/usb.h> #include <soc/usb.h>
#define MAX_PCIE_PORTS 6
#define CLKREQ_DISABLED 0xf #define CLKREQ_DISABLED 0xf
#define APOLLOLAKE_I2C_DEV_MAX 8 #define APOLLOLAKE_I2C_DEV_MAX 8
@ -43,12 +44,7 @@ struct soc_intel_apollolake_config {
* four CLKREQ inputs, but six root ports. Root ports without an * four CLKREQ inputs, but six root ports. Root ports without an
* associated CLKREQ signal must be marked with "CLKREQ_DISABLED" * associated CLKREQ signal must be marked with "CLKREQ_DISABLED"
*/ */
uint8_t pcie_rp0_clkreq_pin; uint8_t pcie_rp_clkreq_pin[MAX_PCIE_PORTS];
uint8_t pcie_rp1_clkreq_pin;
uint8_t pcie_rp2_clkreq_pin;
uint8_t pcie_rp3_clkreq_pin;
uint8_t pcie_rp4_clkreq_pin;
uint8_t pcie_rp5_clkreq_pin;
/* [14:8] DDR mode Number of dealy elements.Each = 125pSec. /* [14:8] DDR mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR mode Number of dealy elements.Each = 125pSec. * [6:0] SDR mode Number of dealy elements.Each = 125pSec.