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Mainboard: Add AMD dinar mainboard. 

Dinar mainboard is an AMD evaluation board for
Orochi Platform family15 model 00-0f processor.

The mainbaord has dual G34 Socket, SR5690/SR5670/SR5650 and SP5100 chipsets.
16 cores InterLagos Opteron processor are supported.
Windows 7 are verified on this platform.

Change-Id: Id97d35e7bca9f0d422841e23f4b762f1ed101ea0
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/564
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
Kerry Sheh 2012-02-07 20:32:34 +08:00 committed by Marc Jones
parent 3c71a8579b
commit 6d6d18efe8
34 changed files with 9786 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/amd/Kconfig
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@ -7,6 +7,8 @@ config BOARD_AMD_DB800
bool "DB800 (Salsa)"
config BOARD_AMD_DBM690T
bool "DBM690T (Herring)"
config BOARD_AMD_DINAR
bool "Dinar"
config BOARD_AMD_MAHOGANY
bool "Mahogany"
config BOARD_AMD_MAHOGANY_FAM10
@ -39,6 +41,7 @@ endchoice
source "src/mainboard/amd/db800/Kconfig"
source "src/mainboard/amd/dbm690t/Kconfig"
source "src/mainboard/amd/dinar/Kconfig"
source "src/mainboard/amd/mahogany/Kconfig"
source "src/mainboard/amd/mahogany_fam10/Kconfig"
source "src/mainboard/amd/norwich/Kconfig"

563
src/mainboard/amd/dinar/BiosCallOuts.c Normal file
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@ -0,0 +1,563 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "agesawrapper.h"
#include "amdlib.h"
#include "BiosCallOuts.h"
#include "Ids.h"
#include "OptionsIds.h"
#include "heapManager.h"
#include "SB700.h"
#ifndef SB_GPIO_REG01
#define SB_GPIO_REG01 1
#endif
#ifndef SB_GPIO_REG24
#define SB_GPIO_REG24 24
#endif
#ifndef SB_GPIO_REG27
#define SB_GPIO_REG27 27
#endif
STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] =
{
{AGESA_ALLOCATE_BUFFER,
BiosAllocateBuffer
},
{AGESA_DEALLOCATE_BUFFER,
BiosDeallocateBuffer
},
{AGESA_DO_RESET,
BiosReset
},
{AGESA_LOCATE_BUFFER,
BiosLocateBuffer
},
{AGESA_READ_SPD,
BiosReadSpd
},
{AGESA_READ_SPD_RECOVERY,
BiosDefaultRet
},
{AGESA_RUNFUNC_ONAP,
BiosRunFuncOnAp
},
{AGESA_GNB_PCIE_SLOT_RESET,
BiosGnbPcieSlotReset
},
{AGESA_GET_IDS_INIT_DATA,
BiosGetIdsInitData
},
{AGESA_HOOKBEFORE_DRAM_INIT,
BiosHookBeforeDramInit
},
{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,
BiosHookBeforeDramInitRecovery
},
{AGESA_HOOKBEFORE_DQS_TRAINING,
BiosHookBeforeDQSTraining
},
{AGESA_HOOKBEFORE_EXIT_SELF_REF,
BiosHookBeforeExitSelfRefresh
},
};
AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
UINTN i;
AGESA_STATUS CalloutStatus;
UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);
for (i = 0; i < CallOutCount; i++)
{
if (BiosCallouts[i].CalloutName == Func)
{
break;
}
}
if(i >= CallOutCount)
{
return AGESA_UNSUPPORTED;
}
CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
return CalloutStatus;
}
CONST IDS_NV_ITEM IdsData[] =
{
/*{
AGESA_IDS_NV_MAIN_PLL_CON,
0x1
},
{
AGESA_IDS_NV_MAIN_PLL_FID_EN,
0x1
},
{
AGESA_IDS_NV_MAIN_PLL_FID,
0x8
},
{
AGESA_IDS_NV_CUSTOM_NB_PSTATE,
},
{
AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL,
},
{
AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL,
},
{
AGESA_IDS_NV_FORCE_NB_PSTATE,
},
*/
{
0xFFFF,
0xFFFF
}
};
#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM))
AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
UINTN i;
IDS_NV_ITEM *IdsPtr;
IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr;
if (Data == IDS_CALLOUT_INIT) {
for (i = 0; i < NUM_IDS_ENTRIES; i++) {
IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue;
IdsPtr[i].IdsNvId = IdsData[i].IdsNvId;
}
}
return AGESA_SUCCESS;
}
AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
UINT32 AvailableHeapSize;
UINT8 *BiosHeapBaseAddr;
UINT32 CurrNodeOffset;
UINT32 PrevNodeOffset;
UINT32 FreedNodeOffset;
UINT32 BestFitNodeOffset;
UINT32 BestFitPrevNodeOffset;
UINT32 NextFreeOffset;
BIOS_BUFFER_NODE *CurrNodePtr;
BIOS_BUFFER_NODE *FreedNodePtr;
BIOS_BUFFER_NODE *BestFitNodePtr;
BIOS_BUFFER_NODE *BestFitPrevNodePtr;
BIOS_BUFFER_NODE *NextFreePtr;
BIOS_HEAP_MANAGER *BiosHeapBasePtr;
AGESA_BUFFER_PARAMS *AllocParams;
AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
AllocParams->BufferPointer = NULL;
AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER);
BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) {
/* First allocation */
CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER);
CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
CurrNodePtr->BufferHandle = AllocParams->BufferHandle;
CurrNodePtr->BufferSize = AllocParams->BufferLength;
CurrNodePtr->NextNodeOffset = 0;
AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE);
/* Update the remaining free space */
FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE);
FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize;
FreedNodePtr->NextNodeOffset = 0;
/* Update the offsets for Allocated and Freed nodes */
BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset;
BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset;
} else {
/* Find out whether BufferHandle has been allocated on the heap. */
/* If it has, return AGESA_BOUNDS_CHK */
CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
while (CurrNodeOffset != 0) {
CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) {
return AGESA_BOUNDS_CHK;
}
CurrNodeOffset = CurrNodePtr->NextNodeOffset;
/* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
to the end of the allocated nodes list.
*/
}
/* Find the node that best fits the requested buffer size */
FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
PrevNodeOffset = FreedNodeOffset;
BestFitNodeOffset = 0;
BestFitPrevNodeOffset = 0;
while (FreedNodeOffset != 0) {
FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
if (BestFitNodeOffset == 0) {
/* First node that fits the requested buffer size */
BestFitNodeOffset = FreedNodeOffset;
BestFitPrevNodeOffset = PrevNodeOffset;
} else {
/* Find out whether current node is a better fit than the previous nodes */
BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) {
BestFitNodeOffset = FreedNodeOffset;
BestFitPrevNodeOffset = PrevNodeOffset;
}
}
}
PrevNodeOffset = FreedNodeOffset;
FreedNodeOffset = FreedNodePtr->NextNodeOffset;
} /* end of while loop */
if (BestFitNodeOffset == 0) {
/* If we could not find a node that fits the requested buffer */
/* size, return AGESA_BOUNDS_CHK */
return AGESA_BOUNDS_CHK;
} else {
BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset);
/* If BestFitNode is larger than the requested buffer, fragment the node further */
if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE);
NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset);
NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE));
NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset;
} else {
/* Otherwise, next free node is NextNodeOffset of BestFitNode */
NextFreeOffset = BestFitNodePtr->NextNodeOffset;
}
/* If BestFitNode is the first buffer in the list, then update
StartOfFreedNodes to reflect the new free node
*/
if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
} else {
BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset;
}
/* Add BestFitNode to the list of Allocated nodes */
CurrNodePtr->NextNodeOffset = BestFitNodeOffset;
BestFitNodePtr->BufferSize = AllocParams->BufferLength;
BestFitNodePtr->BufferHandle = AllocParams->BufferHandle;
BestFitNodePtr->NextNodeOffset = 0;
/* Remove BestFitNode from list of Freed nodes */
AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE);
}
}
return AGESA_SUCCESS;
}
AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
UINT8 *BiosHeapBaseAddr;
UINT32 AllocNodeOffset;
UINT32 PrevNodeOffset;
UINT32 NextNodeOffset;
UINT32 FreedNodeOffset;
UINT32 EndNodeOffset;
BIOS_BUFFER_NODE *AllocNodePtr;
BIOS_BUFFER_NODE *PrevNodePtr;
BIOS_BUFFER_NODE *FreedNodePtr;
BIOS_BUFFER_NODE *NextNodePtr;
BIOS_HEAP_MANAGER *BiosHeapBasePtr;
AGESA_BUFFER_PARAMS *AllocParams;
BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
/* Find target node to deallocate in list of allocated nodes.
Return AGESA_BOUNDS_CHK if the BufferHandle is not found
*/
AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
PrevNodeOffset = AllocNodeOffset;
while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) {
if (AllocNodePtr->NextNodeOffset == 0) {
return AGESA_BOUNDS_CHK;
}
PrevNodeOffset = AllocNodeOffset;
AllocNodeOffset = AllocNodePtr->NextNodeOffset;
AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
}
/* Remove target node from list of allocated nodes */
PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
/* Zero out the buffer, and clear the BufferHandle */
LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader));
AllocNodePtr->BufferHandle = 0;
AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE);
/* Add deallocated node in order to the list of freed nodes */
FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize;
if (AllocNodeOffset < FreedNodeOffset) {
/* Add to the start of the freed list */
if (EndNodeOffset == FreedNodeOffset) {
/* If the freed node is adjacent to the first node in the list, concatenate both nodes */
AllocNodePtr->BufferSize += FreedNodePtr->BufferSize;
AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset;
/* Clear the BufferSize and NextNodeOffset of the previous first node */
FreedNodePtr->BufferSize = 0;
FreedNodePtr->NextNodeOffset = 0;
} else {
/* Otherwise, add freed node to the start of the list
Update NextNodeOffset and BufferSize to include the
size of BIOS_BUFFER_NODE
*/
AllocNodePtr->NextNodeOffset = FreedNodeOffset;
}
/* Update StartOfFreedNodes to the new first node */
BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
} else {
/* Traverse list of freed nodes to find where the deallocated node
should be place
*/
NextNodeOffset = FreedNodeOffset;
NextNodePtr = FreedNodePtr;
while (AllocNodeOffset > NextNodeOffset) {
PrevNodeOffset = NextNodeOffset;
if (NextNodePtr->NextNodeOffset == 0) {
break;
}
NextNodeOffset = NextNodePtr->NextNodeOffset;
NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
}
/* If deallocated node is adjacent to the next node,
concatenate both nodes
*/
if (NextNodeOffset == EndNodeOffset) {
NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset;
NextNodePtr->BufferSize = 0;
NextNodePtr->NextNodeOffset = 0;
} else {
/*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */
AllocNodePtr->NextNodeOffset = NextNodeOffset;
}
/* If deallocated node is adjacent to the previous node,
concatenate both nodes
*/
PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
if (AllocNodeOffset == EndNodeOffset) {
PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
AllocNodePtr->BufferSize = 0;
AllocNodePtr->NextNodeOffset = 0;
} else {
PrevNodePtr->NextNodeOffset = AllocNodeOffset;
}
}
return AGESA_SUCCESS;
}
AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
UINT32 AllocNodeOffset;
UINT8 *BiosHeapBaseAddr;
BIOS_BUFFER_NODE *AllocNodePtr;
BIOS_HEAP_MANAGER *BiosHeapBasePtr;
AGESA_BUFFER_PARAMS *AllocParams;
AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) {
if (AllocNodePtr->NextNodeOffset == 0) {
AllocParams->BufferPointer = NULL;
AllocParams->BufferLength = 0;
return AGESA_BOUNDS_CHK;
} else {
AllocNodeOffset = AllocNodePtr->NextNodeOffset;
AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
}
}
AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE));
AllocParams->BufferLength = AllocNodePtr->BufferSize;
return AGESA_SUCCESS;
}
AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr);
return Status;
}
AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
UINT8 Value;
UINTN ResetType;
AMD_CONFIG_PARAMS *StdHeader;
ResetType = Data;
StdHeader = ConfigPtr;
//
// Perform the RESET based upon the ResetType. In case of
// WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
// AmdResetManager. During the critical condition, where reset is required
// immediately, the reset will be invoked directly by writing 0x04 to port
// 0xCF9 (Reset Port).
//
switch (ResetType) {
case WARM_RESET_WHENEVER:
case COLD_RESET_WHENEVER:
break;
case WARM_RESET_IMMEDIATELY:
case COLD_RESET_IMMEDIATELY:
Value = 0x06;
LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
break;
default:
break;
}
Status = 0;
return Status;
}
AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr);
return Status;
}
AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
return AGESA_UNSUPPORTED;
}
/* Call the host environment interface to provide a user hook opportunity. */
AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
return AGESA_SUCCESS;
}
/* Call the host environment interface to provide a user hook opportunity. */
AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
UINTN FcnData;
MEM_DATA_STRUCT *MemData;
UINT32 AcpiMmioAddr;
UINT32 GpioMmioAddr;
UINT8 Data8;
UINT16 Data16;
UINT8 TempData8;
FcnData = Data;
MemData = ConfigPtr;
Status = AGESA_SUCCESS;
/* Get SB MMIO Base (AcpiMmioAddr) */
WriteIo8 (0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16 = Data8<<8;
WriteIo8 (0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
Status = AGESA_SUCCESS;
return Status;
}
/* Call the host environment interface to provide a user hook opportunity. */
AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
return AGESA_SUCCESS;
}
/* Call the host environment interface to provide a user hook opportunity. */
AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
return AGESA_SUCCESS;
}
/* PCIE slot reset control */
AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
Status = AGESA_SUCCESS;
return Status;
}

79
src/mainboard/amd/dinar/BiosCallOuts.h Normal file
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@ -0,0 +1,79 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _BIOS_CALLOUT_H_
#define _BIOS_CALLOUT_H_
#include "Porting.h"
#include "AGESA.h"
#define BIOS_HEAP_START_ADDRESS 0x00010000
#define BIOS_HEAP_SIZE 0x20000 /* 64MB */
typedef struct _BIOS_HEAP_MANAGER {
//UINT32 AvailableSize;
UINT32 StartOfAllocatedNodes;
UINT32 StartOfFreedNodes;
} BIOS_HEAP_MANAGER;
typedef struct _BIOS_BUFFER_NODE {
UINT32 BufferHandle;
UINT32 BufferSize;
UINT32 NextNodeOffset;
} BIOS_BUFFER_NODE;
/*
* CALLOUTS
*/
AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
/* REQUIRED CALLOUTS
* AGESA ADVANCED CALLOUTS - CPU
*/
AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
/* AGESA ADVANCED CALLOUTS - MEMORY */
AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr);
/* BIOS DEFAULT RET */
AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
/* Call the host environment interface to provide a user hook opportunity. */
AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
/* Call the host environment interface to provide a user hook opportunity. */
AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
/* Call the host environment interface to provide a user hook opportunity. */
AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
/* Call the host environment interface to provide a user hook opportunity. */
AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
/* PCIE slot reset control */
AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
#define SB_GPIO_REG02 2
#define SB_GPIO_REG09 9
#define SB_GPIO_REG10 10
#define SB_GPIO_REG15 15
#define SB_GPIO_REG17 17
#define SB_GPIO_REG21 21
#define SB_GPIO_REG25 25
#define SB_GPIO_REG28 28
#endif //_BIOS_CALLOUT_H_

203
src/mainboard/amd/dinar/Kconfig Normal file
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@ -0,0 +1,203 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
if BOARD_AMD_DINAR
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
select CPU_AMD_AGESA_FAMILY15
select CPU_AMD_SOCKET_G34
select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX
select NORTHBRIDGE_AMD_AGESA_FAMILY15
select NORTHBRIDGE_AMD_CIMX_RD890
select SOUTHBRIDGE_AMD_CIMX_SB700
select SUPERIO_SMSC_SCH4037
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select BOARD_ROMSIZE_KB_2048
select BOARD_HAS_FADT
select HAVE_BUS_CONFIG
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_MAINBOARD_RESOURCES
select HAVE_HARD_RESET
select HAVE_ACPI_TABLES
#TODO select HAVE_ACPI_RESUME
select ENABLE_APIC_EXT_ID
select TINY_BOOTBLOCK
select GFXUMA
config MAINBOARD_DIR
string
default amd/dinar
config APIC_ID_OFFSET
hex
default 0x0
config MAINBOARD_PART_NUMBER
string
default "Dinar"
config HW_MEM_HOLE_SIZEK
hex
default 0x200000
config MAX_CPUS
int
default 64
config MAX_PHYSICAL_CPUS
int
default 16
config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n
config IRQ_SLOT_COUNT
int
default 11
config RAMTOP
hex
default 0x1000000
config HEAP_SIZE
hex
default 0xc0000
config STACK_SIZE
hex
default 0x10000
config ACPI_SSDTX_NUM
int
default 0
config RAMBASE
hex
default 0x200000
config SIO_PORT
hex
default 0x2e
config DRIVERS_PS2_KEYBOARD
bool
default y
config WARNINGS_ARE_ERRORS
bool
default n
config ONBOARD_VGA_IS_PRIMARY
bool
default y
config VGA_BIOS
bool
default n
config VGA_BIOS_ID
depends on VGA_BIOS
default "1002,515e"
config AHCI_BIOS
bool
default y
config AHCI_BIOS_FILE
string "AHCI ROM path and filename"
depends on AHCI_BIOS
default "site-local/ahci/sb700.bin"
config AHCI_BIOS_ID
string "AHCI device PCI IDs"
depends on AHCI_BIOS
default "1002,4391"
config XHC_BIOS
bool
default n
config XHC_BIOS_FILE
string "XHC BIOS path and filename"
depends on XHC_BIOS
default "site-local/xhc/Xhc.rom"
config XHC_BIOS_ID
string "XHC device PCI IDs"
depends on XHC_BIOS
default "1022,7812"
config CONSOLE_POST
bool
depends on !NO_POST
default n
config SATA_CONTROLLER_MODE
hex
default 0x0
depends on SOUTHBRIDGE_AMD_CIMX_SB700
config ONBOARD_LAN
bool
default y
config ONBOARD_1394
bool
default y
config ONBOARD_USB30
bool
default n
config ONBOARD_BLUETOOTH
bool
default y
config ONBOARD_WEBCAM
bool
default y
config ONBOARD_TRAVIS
bool
default y
config ONBOARD_LIGHTSENSOR
bool
default n
config PCI_ROM_RUN
bool
default n
config UDELAY_IO
bool
default n
config REDIRECT_CIMX_TRACE_TO_SERIAL
bool "Redirect CIMX Trace to serial console"
default y
endif # BOARD_AMD_DINAR

38
src/mainboard/amd/dinar/Makefile.inc Normal file
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#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += dimmSpd.c
romstage-y += BiosCallOuts.c
romstage-y += sb700_cfg.c
romstage-y += rd890_cfg.c
ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
ramstage-y += dimmSpd.c
ramstage-y += BiosCallOuts.c
ramstage-y += sb700_cfg.c
ramstage-y += rd890_cfg.c
ramstage-y += reset.c
AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa
AGESA_ROOT ?= $(AGESA_PREFIX)/$(if $(CONFIG_CPU_AMD_AGESA_FAMILY15),f15,\
echo `wrong configuration`)

79
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _AMD_SB_CIMx_OEM_H_
#define _AMD_SB_CIMx_OEM_H_
#define MOVE_PCIEBAR_TO_F0000000
#define LEGACY_FREE 0x00
/**
* PCIEX_BASE_ADDRESS - Define PCIE base address
*
* @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000
*/
#ifdef MOVE_PCIEBAR_TO_F0000000
#define PCIEX_BASE_ADDRESS 0xF8000000
#else
#define PCIEX_BASE_ADDRESS 0xE0000000
#endif
#define SMBUS0_BASE_ADDRESS 0xB00
#define SMBUS1_BASE_ADDRESS 0xB20
#define SIO_PME_BASE_ADDRESS 0xE00
#define SPI_BASE_ADDRESS 0xFEC10000
#define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address
#define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address
#define PM1_EVT_BLK_ADDRESS 0x800 // AcpiPm1EvtBlkAddr;
#define PM1_CNT_BLK_ADDRESS 0x804 // AcpiPm1CntBlkAddr;
#define PM1_TMR_BLK_ADDRESS 0x808 // AcpiPmTmrBlkAddr;
#define CPU_CNT_BLK_ADDRESS 0x810 // CpuControlBlkAddr;
#define GPE0_BLK_ADDRESS 0x820 // AcpiGpe0BlkAddr;
#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr;
#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr;
#define EC_LDN5_MAILBOX_ADDRESS 0x550
#define EC_LDN5_IRQ 0x05
#define EC_LDN9_MAILBOX_ADDRESS 0x3E
#define SATA_IDE_MODE_SSID 0x43901002
#define SATA_RAID_MODE_SSID 0x43921002
#define SATA_RAID5_MODE_SSID 0x43931002
#define SATA_AHCI_SSID 0x43911002
#define OHCI0_SSID 0x43971002
#define OHCI1_SSID 0x43981002
#define EHCI0_SSID 0x43961002
#define OHCI2_SSID 0x43971002
#define OHCI3_SSID 0x43981002
#define EHCI1_SSID 0x43961002
#define OHCI4_SSID 0x43991002
#define SMBUS_SSID 0x43851002
#define IDE_SSID 0x439C1002
#define AZALIA_SSID 0x43831002
#define LPC_SSID 0x439D1002
#define P2P_SSID 0x43841002
#define RESERVED_VALUE 0x00
#endif //ifndef _AMD_SB_CIMx_OEM_H_

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/**
* @file
*
* IDS Option File
*
* This file is used to switch on/off IDS features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $
*/
#ifndef _OPTION_IDS_H_
#define _OPTION_IDS_H_
/**
*
* This file generates the defaults tables for the Integrated Debug Support
* Module. The documented build options are imported from a user controlled
* file for processing. The build options for the Integrated Debug Support
* Module are listed below:
*
* IDSOPT_IDS_ENABLED
* IDSOPT_ERROR_TRAP_ENABLED
* IDSOPT_CONTROL_ENABLED
* IDSOPT_TRACING_ENABLED
* IDSOPT_PERF_ANALYSIS
* IDSOPT_ASSERT_ENABLED
* IDS_DEBUG_PORT
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
*
**/
//#define IDSOPT_IDS_ENABLED TRUE
//#define IDSOPT_TRACING_ENABLED TRUE
#define IDSOPT_ASSERT_ENABLED TRUE
//#define IDSOPT_DEBUG_ENABLED FALSE
//#undef IDSOPT_HOST_SIMNOW
//#define IDSOPT_HOST_SIMNOW FALSE
//#undef IDSOPT_HOST_HDT
//#define IDSOPT_HOST_HDT FALSE
//#define IDS_DEBUG_PORT 0x80
#endif

74
src/mainboard/amd/dinar/acpi/cpstate.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This file defines the processor and performance state capability
* for each core in the system. It is included into the DSDT for each
* core. It assumes that each core of the system has the same performance
* characteristics.
*/
/*
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
{
Scope (\_PR) {
Processor(CPU0,0,0x808,0x06) {
#include "cpstate.asl"
}
Processor(CPU1,1,0x0,0x0) {
#include "cpstate.asl"
}
Processor(CPU2,2,0x0,0x0) {
#include "cpstate.asl"
}
Processor(CPU3,3,0x0,0x0) {
#include "cpstate.asl"
}
}
*/
/* P-state support: The maximum number of P-states supported by the */
/* CPUs we'll use is 6. */
Name(_PSS, Package(){
Package ()
{
0x00000AF0,
0x0000BF81,
0x00000002,
0x00000002,
0x00000000,
0x00000000
},
Package ()
{
0x00000578,
0x000076F2,
0x00000002,
0x00000002,
0x00000001,
0x00000001
}
})
Name(_PCT, Package(){
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
})
Method(_PPC, 0){
Return(0)
}

244
src/mainboard/amd/dinar/acpi/ide.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
Scope (_SB) {
Device(PCI0) {
Device(IDEC) {
Name(_ADR, 0x00140001)
#include "ide.asl"
}
}
}
*/
/* Some timing tables */
Name(UDTT, Package(){ /* Udma timing table */
120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
})
Name(MDTT, Package(){ /* MWDma timing table */
480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
})
Name(POTT, Package(){ /* Pio timing table */
600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
})
/* Some timing register value tables */
Name(MDRT, Package(){ /* MWDma timing register table */
0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
})
Name(PORT, Package(){
0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
})
OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
Field(ICRG, AnyAcc, NoLock, Preserve)
{
PPTS, 8, /* Primary PIO Slave Timing */
PPTM, 8, /* Primary PIO Master Timing */
OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
PMTM, 8, /* Primary MWDMA Master Timing */
OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
PPSM, 4, /* Primary PIO slave Mode */
OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
PDSM, 4, /* Primary UltraDMA Mode */
}
Method(GTTM, 1) /* get total time*/
{
Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
Increment(Local0)
Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
Increment(Local1)
Return(Multiply(30, Add(Local0, Local1)))
}
Device(PRID)
{
Name (_ADR, Zero)
Method(_GTM, 0)
{
NAME(OTBF, Buffer(20) { /* out buffer */
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
})
CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
/* Just return if the channel is disabled */
If(And(PPCR, 0x01)) { /* primary PIO control */
Return(OTBF)
}
/* Always tell them independent timing available and IOChannelReady used on both drives */
Or(BFFG, 0x1A, BFFG)
Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
If(And(PDCR, 0x01)) { /* It's under UDMA mode */
Or(BFFG, 0x01, BFFG)
Store(DerefOf(Index(UDTT, PDMM)), DSD0)
}
Else {
Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
}
If(And(PDCR, 0x02)) { /* It's under UDMA mode */
Or(BFFG, 0x04, BFFG)
Store(DerefOf(Index(UDTT, PDSM)), DSD1)
}
Else {
Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
}
Return(OTBF) /* out buffer */
} /* End Method(_GTM) */
Method(_STM, 3, NotSerialized)
{
NAME(INBF, Buffer(20) { /* in buffer */
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
})
CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
CreateDwordField(INBF, 16, BFFG) /*buffer flag */
Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
Divide(Local0, 7, PDMM,)
Or(PDCR, 0x01, PDCR)
}
Else {
If(LNotEqual(DSD0, 0xFFFFFFFF)) {
Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
Store(DerefOf(Index(MDRT, Local0)), PMTM)
}
}
If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
Divide(Local0, 7, PDSM,)
Or(PDCR, 0x02, PDCR)
}
Else {
If(LNotEqual(DSD1, 0xFFFFFFFF)) {
Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
Store(DerefOf(Index(MDRT, Local0)), PMTS)
}
}
/* Return(INBF) */
} /*End Method(_STM) */
Device(MST)
{
Name(_ADR, 0)
Method(_GTF) {
Name(CMBF, Buffer(21) {
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
})
CreateByteField(CMBF, 1, POMD)
CreateByteField(CMBF, 8, DMMD)
CreateByteField(CMBF, 5, CMDA)
CreateByteField(CMBF, 12, CMDB)
CreateByteField(CMBF, 19, CMDC)
Store(0xA0, CMDA)
Store(0xA0, CMDB)
Store(0xA0, CMDC)
Or(PPMM, 0x08, POMD)
If(And(PDCR, 0x01)) {
Or(PDMM, 0x40, DMMD)
}
Else {
Store(Match
(MDTT, MLE, GTTM(PMTM),
MTR, 0, 0), Local0)
If(LLess(Local0, 3)) {
Or(0x20, Local0, DMMD)
}
}
Return(CMBF)
}
} /* End Device(MST) */
Device(SLAV)
{
Name(_ADR, 1)
Method(_GTF) {
Name(CMBF, Buffer(21) {
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
})
CreateByteField(CMBF, 1, POMD)
CreateByteField(CMBF, 8, DMMD)
CreateByteField(CMBF, 5, CMDA)
CreateByteField(CMBF, 12, CMDB)
CreateByteField(CMBF, 19, CMDC)
Store(0xB0, CMDA)
Store(0xB0, CMDB)
Store(0xB0, CMDC)
Or(PPSM, 0x08, POMD)
If(And(PDCR, 0x02)) {
Or(PDSM, 0x40, DMMD)
}
Else {
Store(Match
(MDTT, MLE, GTTM(PMTS),
MTR, 0, 0), Local0)
If(LLess(Local0, 3)) {
Or(0x20, Local0, DMMD)
}
}
Return(CMBF)
}
} /* End Device(SLAV) */
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
)
{
#include "routing.asl"
}
*/
/* Routing is in System Bus scope */
Scope(\_SB) {
Name(PR0, Package(){
/* NB devices */
/* Bus 0, Dev 0 - RS780 Host Controller */
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
Package(){0x0001FFFF, 0, INTC, 0 },
Package(){0x0001FFFF, 1, INTD, 0 },
/* Bus 0, Dev 2 - */
Package(){0x0002FFFF, 0, INTC, 0 },
Package(){0x0002FFFF, 1, INTD, 0 },
Package(){0x0002FFFF, 2, INTA, 0 },
Package(){0x0002FFFF, 3, INTB, 0 },
/* Bus 0, Dev 3 - */
Package(){0x0003FFFF, 0, INTD, 0 },
Package(){0x0003FFFF, 1, INTA, 0 },
Package(){0x0003FFFF, 2, INTB, 0 },
Package(){0x0003FFFF, 3, INTC, 0 },
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
Package(){0x0004FFFF, 0, INTA, 0 },
Package(){0x0004FFFF, 1, INTB, 0 },
Package(){0x0004FFFF, 2, INTC, 0 },
Package(){0x0004FFFF, 3, INTD, 0 },
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
Package(){0x0005FFFF, 0, INTB, 0 },
Package(){0x0005FFFF, 1, INTC, 0 },
Package(){0x0005FFFF, 2, INTD, 0 },
Package(){0x0005FFFF, 3, INTA, 0 },
/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
Package(){0x0006FFFF, 0, INTC, 0 },
Package(){0x0006FFFF, 1, INTD, 0 },
Package(){0x0006FFFF, 2, INTA, 0 },
Package(){0x0006FFFF, 3, INTB, 0 },
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
Package(){0x0007FFFF, 0, INTD, 0 },
Package(){0x0007FFFF, 1, INTA, 0 },
Package(){0x0007FFFF, 2, INTB, 0 },
Package(){0x0007FFFF, 3, INTC, 0 },
/* SB devices */
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
Package(){0x0014FFFF, 0, INTA, 0 },
Package(){0x0014FFFF, 1, INTB, 0 },
Package(){0x0014FFFF, 2, INTC, 0 },
Package(){0x0014FFFF, 3, INTD, 0 },
/* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI */
Package(){0x0012FFFF, 0, INTC, 0 },
Package(){0x0012FFFF, 1, INTB, 0 },
Package(){0x0013FFFF, 0, INTC, 0 },
Package(){0x0013FFFF, 1, INTB, 0 },
Package(){0x0016FFFF, 0, INTC, 0 },
Package(){0x0016FFFF, 1, INTB, 0 },
Package(){0x0010FFFF, 0, INTC, 0 },
Package(){0x0010FFFF, 1, INTB, 0 },
/* Bus 0, Dev 17 - SATA controller #2 */
Package(){0x0011FFFF, 0, INTD, 0 },
/* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */
Package(){0x0015FFFF, 0, INTA, 0 },
Package(){0x0015FFFF, 1, INTB, 0 },
Package(){0x0015FFFF, 2, INTC, 0 },
Package(){0x0015FFFF, 3, INTD, 0 },
})
Name(APR0, Package(){
/* NB devices in APIC mode */
/* Bus 0, Dev 0 - RS780 Host Controller */
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
Package(){0x0001FFFF, 0, 0, 18 },
Package(){0x0001FFFF, 1, 0, 19 },
/* Bus 0, Dev 2 */
Package(){0x0002FFFF, 0, 0, 18 },
Package(){0x0002FFFF, 1, 0, 19 },
Package(){0x0002FFFF, 2, 0, 16 },
Package(){0x0002FFFF, 3, 0, 17 },
/* Bus 0, Dev 3 */
Package(){0x0003FFFF, 0, 0, 19 },
Package(){0x0003FFFF, 1, 0, 16 },
Package(){0x0003FFFF, 2, 0, 17 },
Package(){0x0003FFFF, 3, 0, 18 },
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
Package(){0x0004FFFF, 0, 0, 16 },
Package(){0x0004FFFF, 1, 0, 17 },
Package(){0x0004FFFF, 2, 0, 18 },
Package(){0x0004FFFF, 3, 0, 19 },
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
Package(){0x0005FFFF, 0, 0, 17 },
Package(){0x0005FFFF, 1, 0, 18 },
Package(){0x0005FFFF, 2, 0, 19 },
Package(){0x0005FFFF, 3, 0, 16 },
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
Package(){0x0006FFFF, 0, 0, 18 },
Package(){0x0006FFFF, 1, 0, 19 },
Package(){0x0006FFFF, 2, 0, 16 },
Package(){0x0006FFFF, 3, 0, 17 },
/* Bus 0, Dev 7 - PCIe Bridge for network card */
Package(){0x0007FFFF, 0, 0, 19 },
Package(){0x0007FFFF, 1, 0, 16 },
Package(){0x0007FFFF, 2, 0, 17 },
Package(){0x0007FFFF, 3, 0, 18 },
/* SB devices in APIC mode */
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
Package(){0x0014FFFF, 0, 0, 16 },
Package(){0x0014FFFF, 1, 0, 17 },
Package(){0x0014FFFF, 2, 0, 18 },
Package(){0x0014FFFF, 3, 0, 19 },
/* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI*/
Package(){0x0012FFFF, 0, 0, 18 },
Package(){0x0012FFFF, 1, 0, 17 },
Package(){0x0013FFFF, 0, 0, 18 },
Package(){0x0013FFFF, 1, 0, 17 },
Package(){0x0016FFFF, 0, 0, 18 },
Package(){0x0016FFFF, 1, 0, 17 },
Package(){0x0010FFFF, 0, 0, 18 },
Package(){0x0010FFFF, 1, 0, 17 },
/* Bus 0, Dev 17 - SATA controller #2 */
Package(){0x0011FFFF, 0, 0, 19 },
/* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */
Package(){0x0015FFFF, 0, 0, 16 },
Package(){0x0015FFFF, 1, 0, 17 },
Package(){0x0015FFFF, 2, 0, 18 },
Package(){0x0015FFFF, 3, 0, 19 },
})
Name(PS2, Package(){
/* For Device(PBR2) PIC mode*/
Package(){0x0000FFFF, 0, INTC, 0 },
Package(){0x0000FFFF, 1, INTD, 0 },
Package(){0x0000FFFF, 2, INTA, 0 },
Package(){0x0000FFFF, 3, INTB, 0 },
})
Name(APS2, Package(){
/* For Device(PBR2) APIC mode*/
Package(){0x0000FFFF, 0, 0, 18 },
Package(){0x0000FFFF, 1, 0, 19 },
Package(){0x0000FFFF, 2, 0, 16 },
Package(){0x0000FFFF, 3, 0, 17 },
})
Name(PS3, Package(){
/* For Device(PBR3) PIC mode*/
Package(){0x0000FFFF, 0, INTD, 0 },
Package(){0x0000FFFF, 1, INTA, 0 },
Package(){0x0000FFFF, 2, INTB, 0 },
Package(){0x0000FFFF, 3, INTC, 0 },
})
Name(APS3, Package(){
/* For Device(PBR3) APIC mode*/
Package(){0x0000FFFF, 0, 0, 19 },
Package(){0x0000FFFF, 1, 0, 16 },
Package(){0x0000FFFF, 2, 0, 17 },
Package(){0x0000FFFF, 3, 0, 18 },
})
Name(PS4, Package(){
/* For Device(PBR4) PIC mode*/
Package(){0x0000FFFF, 0, INTA, 0 },
Package(){0x0000FFFF, 1, INTB, 0 },
Package(){0x0000FFFF, 2, INTC, 0 },
Package(){0x0000FFFF, 3, INTD, 0 },
})
Name(APS4, Package(){
/* For Device(PBR4) APIC mode*/
Package(){0x0000FFFF, 0, 0, 16 },
Package(){0x0000FFFF, 1, 0, 17 },
Package(){0x0000FFFF, 2, 0, 18 },
Package(){0x0000FFFF, 3, 0, 19 },
})
Name(PS5, Package(){
/* For Device(PBR5) PIC mode*/
Package(){0x0000FFFF, 0, INTB, 0 },
Package(){0x0000FFFF, 1, INTC, 0 },
Package(){0x0000FFFF, 2, INTD, 0 },
Package(){0x0000FFFF, 3, INTA, 0 },
})
Name(APS5, Package(){
/* For Device(PBR5) APIC mode*/
Package(){0x0000FFFF, 0, 0, 17 },
Package(){0x0000FFFF, 1, 0, 18 },
Package(){0x0000FFFF, 2, 0, 19 },
Package(){0x0000FFFF, 3, 0, 16 },
})
Name(PS6, Package(){
/* For Device(PBR6) PIC mode*/
Package(){0x0000FFFF, 0, INTC, 0 },
Package(){0x0000FFFF, 1, INTD, 0 },
Package(){0x0000FFFF, 2, INTA, 0 },
Package(){0x0000FFFF, 3, INTB, 0 },
})
Name(APS6, Package(){
/* For Device(PBR6) APIC mode*/
Package(){0x0000FFFF, 0, 0, 18 },
Package(){0x0000FFFF, 1, 0, 19 },
Package(){0x0000FFFF, 2, 0, 16 },
Package(){0x0000FFFF, 3, 0, 17 },
})
Name(PS7, Package(){
/* For Device(PBR7) PIC mode*/
Package(){0x0000FFFF, 0, INTD, 0 },
Package(){0x0000FFFF, 1, INTA, 0 },
Package(){0x0000FFFF, 2, INTB, 0 },
Package(){0x0000FFFF, 3, INTC, 0 },
})
Name(APS7, Package(){
/* For Device(PBR7) APIC mode*/
Package(){0x0000FFFF, 0, 0, 19 },
Package(){0x0000FFFF, 1, 0, 16 },
Package(){0x0000FFFF, 2, 0, 17 },
Package(){0x0000FFFF, 3, 0, 18 },
})
Name(PE0, Package(){
/* For Device(PE20) PIC mode*/
Package(){0x0000FFFF, 0, INTA, 0 },
Package(){0x0000FFFF, 1, INTB, 0 },
Package(){0x0000FFFF, 2, INTC, 0 },
Package(){0x0000FFFF, 3, INTD, 0 },
})
Name(APE0, Package(){
/* For Device(PE20) APIC mode*/
Package(){0x0000FFFF, 0, 0, 16 },
Package(){0x0000FFFF, 1, 0, 17 },
Package(){0x0000FFFF, 2, 0, 18 },
Package(){0x0000FFFF, 3, 0, 19 },
})
Name(PE1, Package(){
/* For Device(PE21) PIC mode*/
Package(){0x0000FFFF, 0, INTB, 0 },
Package(){0x0000FFFF, 1, INTC, 0 },
Package(){0x0000FFFF, 2, INTD, 0 },
Package(){0x0000FFFF, 3, INTA, 0 },
})
Name(APE1, Package(){
/* For Device(PE21) APIC mode*/
Package(){0x0000FFFF, 0, 0, 17 },
Package(){0x0000FFFF, 1, 0, 18 },
Package(){0x0000FFFF, 2, 0, 19 },
Package(){0x0000FFFF, 3, 0, 16 },
})
Name(PE2, Package(){
/* For Device(PE22) PIC mode*/
Package(){0x0000FFFF, 0, INTC, 0 },
Package(){0x0000FFFF, 1, INTD, 0 },
Package(){0x0000FFFF, 2, INTA, 0 },
Package(){0x0000FFFF, 3, INTB, 0 },
})
Name(APE2, Package(){
/* For Device(PE22) APIC mode*/
Package(){0x0000FFFF, 0, 0, 18 },
Package(){0x0000FFFF, 1, 0, 19 },
Package(){0x0000FFFF, 2, 0, 16 },
Package(){0x0000FFFF, 3, 0, 17 },
})
Name(PE3, Package(){
/* For Device(PE23) PIC mode*/
Package(){0x0000FFFF, 0, INTD, 0 },
Package(){0x0000FFFF, 1, INTA, 0 },
Package(){0x0000FFFF, 2, INTB, 0 },
Package(){0x0000FFFF, 3, INTC, 0 },
})
Name(APE3, Package(){
/* For Device(PE23) APIC mode*/
Package(){0x0000FFFF, 0, 0, 19 },
Package(){0x0000FFFF, 1, 0, 16 },
Package(){0x0000FFFF, 2, 0, 17 },
Package(){0x0000FFFF, 3, 0, 18 },
})
}

149
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* simple name description */
/*
Scope (_SB) {
Device(PCI0) {
Device(SATA) {
Name(_ADR, 0x00110000)
#include "sata.asl"
}
}
}
*/
Name(STTM, Buffer(20) {
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
0x1f, 0x00, 0x00, 0x00
})
/* Start by clearing the PhyRdyChg bits */
Method(_INI) {
\_GPE._L1F()
}
Device(PMRY)
{
Name(_ADR, 0)
Method(_GTM, 0x0, NotSerialized) {
Return(STTM)
}
Method(_STM, 0x3, NotSerialized) {}
Device(PMST) {
Name(_ADR, 0)
Method(_STA,0) {
if (LGreater(P0IS,0)) {
return (0x0F) /* sata is visible */
}
else {
return (0x00) /* sata is missing */
}
}
}/* end of PMST */
Device(PSLA)
{
Name(_ADR, 1)
Method(_STA,0) {
if (LGreater(P1IS,0)) {
return (0x0F) /* sata is visible */
}
else {
return (0x00) /* sata is missing */
}
}
} /* end of PSLA */
} /* end of PMRY */
Device(SEDY)
{
Name(_ADR, 1) /* IDE Scondary Channel */
Method(_GTM, 0x0, NotSerialized) {
Return(STTM)
}
Method(_STM, 0x3, NotSerialized) {}
Device(SMST)
{
Name(_ADR, 0)
Method(_STA,0) {
if (LGreater(P2IS,0)) {
return (0x0F) /* sata is visible */
}
else {
return (0x00) /* sata is missing */
}
}
} /* end of SMST */
Device(SSLA)
{
Name(_ADR, 1)
Method(_STA,0) {
if (LGreater(P3IS,0)) {
return (0x0F) /* sata is visible */
}
else {
return (0x00) /* sata is missing */
}
}
} /* end of SSLA */
} /* end of SEDY */
/* SATA Hot Plug Support */
Scope(\_GPE) {
Method(_L1F,0x0,NotSerialized) {
if (\_SB.P0PR) {
if (LGreater(\_SB.P0IS,0)) {
sleep(32)
}
Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
store(one, \_SB.P0PR)
}
if (\_SB.P1PR) {
if (LGreater(\_SB.P1IS,0)) {
sleep(32)
}
Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
store(one, \_SB.P1PR)
}
if (\_SB.P2PR) {
if (LGreater(\_SB.P2IS,0)) {
sleep(32)
}
Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
store(one, \_SB.P2PR)
}
if (\_SB.P3PR) {
if (LGreater(\_SB.P3IS,0)) {
sleep(32)
}
Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
store(one, \_SB.P3PR)
}
}
}

320
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <arch/ioapic.h>
#include <arch/io.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include "agesawrapper.h"
#define DUMP_ACPI_TABLES 0
#if DUMP_ACPI_TABLES == 1
static void dump_mem(u32 start, u32 end)
{
u32 i;
print_debug("dump_mem:");
for (i = start; i < end; i++) {
if ((i & 0xf) == 0) {
printk(BIOS_DEBUG, "\n%08x:", i);
}
printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
}
print_debug("\n");
}
#endif
extern const unsigned char AmlCode[];
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
return current;
}
unsigned long acpi_fill_madt(unsigned long current)
{
device_t dev;
u32 dword;
u32 gsi_base = 0;
u32 apicid_sb700;
u32 apicid_rd890;
/*
* AGESA v5 Apply apic enumeration rules
* For systems with >= 16 APICs, put the IO-APICs at 0..n and
* put the local-APICs at m..z
* For systems with < 16 APICs, put the Local-APICs at 0..n and
* put the IO-APICs at (n + 1)..z
*/
#if CONFIG_MAX_CPUS >= 16
apicid_sb700 = 0x0;
#else
apicid_sb700 = CONFIG_MAX_CPUS + 1
#endif
apicid_rd890 = apicid_sb700 + 1;
/* create all subtables for processors */
current = acpi_create_madt_lapics(current);
/* Write sb700 IOAPIC, only one */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
apicid_sb700,
IO_APIC_ADDR,
0
);
/* IOAPIC on rs5690 */
gsi_base += IO_APIC_INTERRUPTS; /* sb700 has 24 IOAPIC entries. */
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (dev) {
pci_write_config32(dev, 0xF8, 0x1);
dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
apicid_rd890,
dword,
gsi_base
);
}
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current,
0, //BUS
0, //SOURCE
2, //gsirq
0 //flags
);
/* 0: mean bus 0--->ISA */
/* 0: PIC 0 */
/* 2: APIC 2 */
/* 5 mean: 0101 --> Edige-triggered, Active high */
/* create all subtables for processors */
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
/* 1: LINT1 connect to NMI */
return current;
}
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
return current;
}
unsigned long acpi_fill_srat(unsigned long current)
{
/* No NUMA, no SRAT */
return current;
}
unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
{
int lens;
msr_t msr;
char pscope[] = "\\_SB.PCI0";
lens = acpigen_write_scope(pscope);
msr = rdmsr(TOP_MEM);
lens += acpigen_write_name_dword("TOM1", msr.lo);
msr = rdmsr(TOP_MEM2);
/*
* Since XP only implements parts of ACPI 2.0, we can't use a qword
* here.
* See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
* slide 22ff.
* Shift value right by 20 bit to make it fit into 32bit,
* giving us 1MB granularity and a limit of almost 4Exabyte of memory.
*/
lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
acpigen_patch_len(lens - 1);
return (unsigned long) (acpigen_get_current());
}
unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt;
//acpi_hpet_t *hpet;
acpi_madt_t *madt;
acpi_srat_t *srat;
acpi_slit_t *slit;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
acpi_header_t *dsdt;
acpi_header_t *ssdt;
acpi_header_t *ssdt2;
acpi_header_t *alib;
get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
/* Align ACPI tables to 16 bytes */
start = (start + 0x0f) & -0x10;
current = start;
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t);
rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t);
/* clear all table memory */
memset((void *)start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt, NULL);
acpi_write_rsdt(rsdt);
/* FACS */
printk(BIOS_DEBUG, "ACPI: * FACS\n");
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
acpi_create_facs(facs);
/* DSDT */
printk(BIOS_DEBUG, "ACPI: * DSDT\n");
dsdt = (acpi_header_t *)current;
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
current += dsdt->length;
memcpy(dsdt, &AmlCode, dsdt->length);
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length);
/* FADT */
printk(BIOS_DEBUG, "ACPI: * FADT\n");
fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);
acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdp, fadt);
/*
* We explicitly add these tables later on:
*/
#ifdef UNUSED_CODE // Don't need HPET table. we have one in dsdt
current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet);
acpi_add_table(rsdp, hpet);
#endif
/* If we want to use HPET Timers Linux wants an MADT */
current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
current += madt->header.length;
acpi_add_table(rsdp, madt);
/* SRAT */
current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
if (srat != NULL) {
memcpy((void *)current, srat, srat->header.length);
srat = (acpi_srat_t *) current;
//acpi_create_srat(srat);
current += srat->header.length;
acpi_add_table(rsdp, srat);
}
/* SLIT */
current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
if (slit != NULL) {
memcpy((void *)current, slit, slit->header.length);
slit = (acpi_slit_t *) current;
//acpi_create_slit(slit);
current += slit->header.length;
acpi_add_table(rsdp, slit);
}
/* SSDT */
current = (current + 0x0f) & -0x10;
printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current);
alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
if (alib != NULL) {
memcpy((void *)current, alib, alib->length);
ssdt = (acpi_header_t *) current;
current += alib->length;
acpi_add_table(rsdp,alib);
} else {
printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n");
}
#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table
current = ( current + 0x0f) & -0x10;
printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current);
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
if (ssdt != NULL) {
memcpy((void *)current, ssdt, ssdt->length);
ssdt = (acpi_header_t *) current;
current += ssdt->length;
} else {
printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n");
}
acpi_add_table(rsdp,ssdt);
#endif
current = ( current + 0x0f) & -0x10;
printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current);
ssdt2 = (acpi_header_t *) current;
acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR);
current += ssdt2->length;
acpi_add_table(rsdp,ssdt2);
#if DUMP_ACPI_TABLES == 1
printk(BIOS_DEBUG, "rsdp\n");
dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
printk(BIOS_DEBUG, "rsdt\n");
dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
printk(BIOS_DEBUG, "madt\n");
dump_mem(madt, ((void *)madt) + madt->header.length);
printk(BIOS_DEBUG, "srat\n");
dump_mem(srat, ((void *)srat) + srat->header.length);
printk(BIOS_DEBUG, "slit\n");
dump_mem(slit, ((void *)slit) + slit->header.length);
printk(BIOS_DEBUG, "ssdt\n");
dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
printk(BIOS_DEBUG, "fadt\n");
dump_mem(fadt, ((void *)fadt) + fadt->header.length);
#endif
printk(BIOS_INFO, "ACPI: done.\n");
return current;
}

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src/mainboard/amd/dinar/agesawrapper.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include <stdint.h>
#include <string.h>
#include "agesawrapper.h"
#include "BiosCallOuts.h"
#include "cpuRegisters.h"
#include "cpuCacheInit.h"
#include "cpuApicUtilities.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "Dispatcher.h"
#include "cpuCacheInit.h"
#include "amdlib.h"
#include "heapManager.h"
#include "Filecode.h"
#include <arch/io.h>
#define FILECODE UNASSIGNED_FILE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/
/*Get the Bus Number from CONFIG_MMCONF_BUS_NUMBER, Please reference AMD BIOS BKDG docuemt about it*/
/*
BusRange: bus range identifier. Read-write. Reset: X. This specifies the number of buses in the
MMIO configuration space range. The size of the MMIO configuration space range varies with this
field as follows: the size is 1 Mbyte times the number of buses. This field is encoded as follows:
Bits Buses Bits Buses
0h 1 5h 32
1h 2 6h 64
2h 4 7h 128
3h 8 8h 256
4h 16 Fh-9h Reserved
*/
UINT8
GetEndBusNum (
VOID
)
{
UINT64 BusNum;
UINT8 Index;
for (Index = 1; Index <= 8; Index ++ ) {
BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
if (BusNum == 1 ) {
break;
}
}
return Index;
}
static UINT32 amdinitcpuio(VOID)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
UINT32 TopMem;
UINT32 NodeCnt;
UINT32 Node;
UINT32 SbLink;
UINT32 Index;
/* get the number of coherent nodes in the system */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x60);
LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
NodeCnt = ((PciData >> 4) & 7) + 1; //NodeCnt[6:4]
/* Find out the Link ID of Node0 that connects to the
* Southbridge (system IO hub). e.g. family10 MCM Processor,
* SbLink is Processor0 Link2, internal Node0 Link3
*/
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x64);
LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
SbLink = (PciData >> 8) & 3; //assume ganged
/* Enable MMIO on AMD CPU Address Map Controller for all nodes */
for (Node = 0; Node < NodeCnt; Node ++) {
/* clear all MMIO Mapped Base/Limit Registers */
for (Index = 0; Index < 8; Index ++) {
PciData = 0x00000000;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0x80 + Index * 8);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0x84 + Index * 8);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
/* clear all IO Space Base/Limit Registers */
for (Index = 0; Index < 4; Index ++) {
PciData = 0x00000000;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0xC0 + Index * 8);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0xC4 + Index * 8);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
/* Enable MMIO on AMD CPU Address Map Controller */
/* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x80);
PciData = (0xA0000 >> 8) |3;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x84);
PciData = 0xB0000 >> 8;
PciData &= (~0xFF);
PciData |= SbLink << 4;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set UMA MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x88);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
TopMem = (UINT32)MsrReg;
MsrReg = (MsrReg >> 8) | 3;
PciData = (UINT32)MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x8c);
if (TopMem <= CONFIG_MMCONF_BASE_ADDRESS) {
PciData = (CONFIG_MMCONF_BASE_ADDRESS - 1) >> 8;
}
else {
PciData = (0x100000000ull - 1) >> 8;
}
PciData &= (~0xFF);
PciData |= SbLink << 4;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set PCIE MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x90);
PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) |3;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x94);
PciData = (( CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 *256 - 1) >> 8) & (~0xFF);
PciData &= (~0xFF);
PciData |= MMIO_NP_BIT;
PciData |= SbLink << 4;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set XAPIC MMIO. 24K */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x98);
PciData = (0xFEC00000 >> 8) |3;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x9c);
PciData = ((0xFEC00000 + 6 * 4096 - 1) >> 8);
PciData &= (~0xFF);
PciData |= MMIO_NP_BIT;
PciData |= SbLink << 4;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set Local APIC MMIO. 4K*4= 16K, Llano CPU are 4 cores */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xA0);
PciData = (0xFEE00000 >> 8) |3;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xA8);
PciData = (0xFEE00000 + 4 * 4096 - 1) >> 8;
PciData &= (~0xFF);
PciData |= MMIO_NP_BIT;
PciData |= SbLink << 4;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set PCIO: 0x0 - 0xFFF000 and enabled VGA IO*/
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xC0);
PciData = 0x13;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xC4);
PciData = 0x00FFF000;
PciData &= (~0x7F);
PciData |= SbLink << 4;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
Status = AGESA_SUCCESS;
return (UINT32)Status;
}
UINT32
agesawrapper_amdinitmmio (
VOID
)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (GetEndBusNum () << 2) | 1;
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | BIT46;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* Set PCIE MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x90);
PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) |3;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x94);
PciData = (( CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 *256 - 1) >> 8) | MMIO_NP_BIT;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Enable memory access */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04);
LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader);
PciData |= BIT1;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04);
LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
LibAmdMsrWrite (0x20E, &MsrReg, &StdHeader);
MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
LibAmdMsrWrite (0x20F, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS;
return (UINT32)Status;
}
UINT32
agesawrapper_amdinitreset (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams,
0,
sizeof (AMD_RESET_PARAMS),
&(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = NULL;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0;
#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE)
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
#endif
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status;
}
UINT32
agesawrapper_amdinitearly (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status;
}
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This is the stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] **PeiServices
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
{
//InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO;
}
VOID
OemCustomizeInitPost (
IN AMD_POST_PARAMS *InitPost
)
{
InitPost->MemConfig.UmaMode = UMA_AUTO;
InitPost->MemConfig.BottomIo = 0xE0;
InitPost->MemConfig.UmaSize = 0xE0-0xC0;
}
UINT32
agesawrapper_amdinitpost (
VOID
)
{
AGESA_STATUS status;
UINT16 i;
UINT32 *HeadPtr;
AMD_INTERFACE_PARAMS AmdParamStruct;
BIOS_HEAP_MANAGER *BiosManagerPtr;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
/* OEM Should Customize the defaults through this hook */
OemCustomizeInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct);
/* Initialize heap space */
BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
{
*HeadPtr = 0x00000000;
HeadPtr++;
}
BiosManagerPtr->StartOfAllocatedNodes = 0;
BiosManagerPtr->StartOfFreedNodes = 0;
return (UINT32)status;
}
UINT32
agesawrapper_amdinitenv (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
PCI_ADDR PciAddress;
UINT32 PciValue;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status;
}
VOID *
agesawrapper_getlateinitptr (
int pick
)
{
switch (pick) {
case PICK_DMI:
return DmiTable;
case PICK_PSTATE:
return AcpiPstate;
case PICK_SRAT:
return AcpiSrat;
case PICK_SLIT:
return AcpiSlit;
case PICK_WHEA_MCE:
return AcpiWheaMce;
case PICK_WHEA_CMC:
return AcpiWheaCmc;
case PICK_ALIB:
return AcpiAlib;
default:
return NULL;
}
}
UINT32
agesawrapper_amdinitmid (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
printk(BIOS_DEBUG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__);
/* Enable MMIO on AMD CPU Address Map Controller */
amdinitcpuio ();
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status;
}
UINT32
agesawrapper_amdinitlate(VOID)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS *AmdLateParamsPtr;
LibAmdMemFill(&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdCreateStruct (&AmdParamStruct);
AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
Status = AmdInitLate(AmdLateParamsPtr);
if (Status != AGESA_SUCCESS) {
//agesawrapper_amdreadeventlog(AmdLateParamsPtr->StdHeader.HeapStatus);
agesawrapper_amdreadeventlog();
ASSERT(Status == AGESA_SUCCESS);
}
DmiTable = AmdLateParamsPtr->DmiTable;
AcpiPstate = AmdLateParamsPtr->AcpiPState;
AcpiSrat = AmdLateParamsPtr->AcpiSrat;
AcpiSlit = AmdLateParamsPtr->AcpiSlit;
AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
AcpiAlib = AmdLateParamsPtr->AcpiAlib;
printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
" DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n"
" Mce:%p\n Cmc:%p\n Alib:%p\n",
__func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
/* Don't release the structure until coreboot has copied the ACPI tables.
* AmdReleaseStruct (&AmdLateParams);
*/
return (UINT32)Status;
}
UINT32
agesawrapper_amdlaterunaptask (
UINT32 Data,
VOID *ConfigPtr
)
{
AGESA_STATUS Status;
AMD_LATE_PARAMS AmdLateParams;
LibAmdMemFill (&AmdLateParams,
0,
sizeof (AMD_LATE_PARAMS),
&(AmdLateParams.StdHeader));
AmdLateParams.StdHeader.AltImageBasePtr = 0;
AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdLateParams.StdHeader.Func = 0;
AmdLateParams.StdHeader.ImageBasePtr = 0;
Status = AmdLateRunApTask (&AmdLateParams);
if (Status != AGESA_SUCCESS) {
agesawrapper_amdreadeventlog();
ASSERT(Status == AGESA_SUCCESS);
}
return (UINT32)Status;
}
UINT32
agesawrapper_amdreadeventlog (
VOID
)
{
AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams,
0,
sizeof (EVENT_PARAMS),
&(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = NULL;
AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0;
Status = AmdReadEventLog (&AmdEventParams);
while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams);
}
return (UINT32)Status;
}

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src/mainboard/amd/dinar/agesawrapper.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#ifndef _AGESAWRAPPER_H_
#define _AGESAWRAPPER_H_
#include <stdint.h>
#include "Porting.h"
#include "AGESA.h"
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/* Define AMD Ontario APPU SSID/SVID */
#define AMD_APU_SVID 0x1022
#define AMD_APU_SSID 0x1234
#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
#define MMIO_NP_BIT BIT7
/* Hudson-2 ACPI PmIO Space Define */
#define SB_ACPI_BASE_ADDRESS 0x0400
#define ACPI_MMIO_BASE 0xFED80000
#define SB_CFG_BASE 0x000 // DWORD
#define GPIO_BASE 0x100 // BYTE
#define SMI_BASE 0x200 // DWORD
#define PMIO_BASE 0x300 // DWORD
#define PMIO2_BASE 0x400 // BYTE
#define BIOS_RAM_BASE 0x500 // BYTE
#define CMOS_RAM_BASE 0x600 // BYTE
#define CMOS_BASE 0x700 // BYTE
#define ASF_BASE 0x900 // DWORD
#define SMBUS_BASE 0xA00 // DWORD
#define WATCHDOG_BASE 0xB00 // ??
#define HPET_BASE 0xC00 // DWORD
#define IOMUX_BASE 0xD00 // BYTE
#define MISC_BASE 0xE00
#define SERIAL_DEBUG_BASE 0x1000
#define GFX_DAC_BASE 0x1400
#define CEC_BASE 0x1800
#define XHCI_BASE 0x1C00
#define ACPI_SMI_DATA_PORT 0xB1
#define R_SB_ACPI_PM1_STATUS 0x00
#define R_SB_ACPI_PM1_ENABLE 0x02
#define R_SB_ACPI_PM_CONTROL 0x04
#define R_SB_ACPI_EVENT_STATUS 0x20
#define R_SB_ACPI_EVENT_ENABLE 0x24
#define B_PWR_BTN_STATUS BIT8
#define B_WAKEUP_STATUS BIT15
#define B_SCI_EN BIT0
#define SB_PM_INDEX_PORT 0xCD6
#define SB_PM_DATA_PORT 0xCD7
#define SB_PMIOA_REG24 0x24 // AcpiMmioEn
#define MmioAddress( BaseAddr, Register ) \
( (UINTN)BaseAddr + \
(UINTN)(Register) \
)
#define Mmio32Ptr( BaseAddr, Register ) \
( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) )
#define Mmio32( BaseAddr, Register ) \
*Mmio32Ptr( BaseAddr, Register )
enum {
PICK_DMI, /* DMI Interface */
PICK_PSTATE, /* Acpi Pstate SSDT Table */
PICK_SRAT, /* SRAT Table */
PICK_SLIT, /* SLIT Table */
PICK_WHEA_MCE, /* WHEA MCE table */
PICK_WHEA_CMC, /* WHEA CMV table */
PICK_ALIB, /* SACPI SSDT table with ALIB implementation */
};
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
typedef struct {
UINT32 CalloutName;
AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr);
} BIOS_CALLOUT_STRUCT;
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/
//void brazos_platform_stage(void);
UINT32 agesawrapper_amdinitreset (void);
UINT32 agesawrapper_amdinitearly (void);
UINT32 agesawrapper_amdinitenv (void);
UINT32 agesawrapper_amdinitlate (void);
UINT32 agesawrapper_amdinitpost (void);
UINT32 agesawrapper_amdinitmid (void);
void sb_After_Pci_Init (void);
void sb_Mid_Post_Init (void);
void sb_Late_Post (void);
UINT32 agesawrapper_amdreadeventlog (void);
UINT32 agesawrapper_amdinitmmio (void);
void *agesawrapper_getlateinitptr (int pick);
#endif

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src/mainboard/amd/dinar/buildOpts.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/**
* @file
*
* AMD User options selection for a Sabine/Lynx platform solution system
*
* This file is placed in the user's platform directory and contains the
* build option selections desired for that platform.
*
* For Information about this file, see @ref platforminstall.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 6049 $ @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
*/
#include "AGESA.h"
#include "CommonReturns.h"
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* Select the cpu family. */
/* Select the cpu socket type. */
#define INSTALL_G34_SOCKET_SUPPORT TURE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
#define INSTALL_FS1_SOCKET_SUPPORT FALSE
#define INSTALL_FM1_SOCKET_SUPPORT FALSE
#define INSTALL_FP1_SOCKET_SUPPORT FALSE
#define INSTALL_FT1_SOCKET_SUPPORT FALSE
#define INSTALL_AM3_SOCKET_SUPPORT FALSE
/*
* Agesa optional capabilities selection.
* Uncomment and mark FALSE those features you wish to include in the build.
* Comment out or mark TRUE those features you want to REMOVE from the build.
*/
/* User makes option selections here
* Comment out the items wanted to be included in the build.
* Uncomment those items you with to REMOVE from the build.
*/
//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
//#define BLDOPT_REMOVE_DDR3_SUPPORT TRUE
//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
//#define BLDOPT_REMOVE_ACPI_PSTATES TRUE
//#define BLDOPT_REMOVE_SRAT TRUE
//#define BLDOPT_REMOVE_SLIT TRUE
#define BLDOPT_REMOVE_WHEA TRUE
//#define BLDOPT_REMOVE_DMI TRUE
#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
//#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
/* Build configuration values here.
*/
#define BLDCFG_VRM_CURRENT_LIMIT 120000
#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
#define BLDCFG_PLAT_NUM_IO_APICS 2
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
#define BLDCFG_MEM_INIT_PSTATE 0
#define BLDCFG_AMD_PSTATE_CAP_VALUE 0
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER
#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY
#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE
#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING TRUE
#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
#define BLDCFG_MEMORY_POWER_DOWN TRUE
#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT //FALSE
#define BLDCFG_ONLINE_SPARE TRUE
#define BLDCFG_MEMORY_PARITY_ENABLE TRUE
#define BLDCFG_BANK_SWIZZLE TRUE
#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
#define BLDCFG_DQS_TRAINING_CONTROL TRUE
#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
#define BLDCFG_USE_BURST_MODE FALSE
#define BLDCFG_MEMORY_ALL_CLOCKS_ON TRUE
#define BLDCFG_ENABLE_ECC_FEATURE TRUE
#define BLDCFG_ECC_REDIRECTION TRUE
#define BLDCFG_SCRUB_IC_RATE 0
#define BLDCFG_ECC_SYNC_FLOOD TRUE
#define BLDCFG_ECC_SYMBOL_SIZE 0
#define BLDCFG_1GB_ALIGN FALSE
#define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased
#define BLDCFG_PLATFORM_C1E_OPDATA 0x2000
//#define BLDCFG_USE_ATM_MODE TRUE
#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0xCB0
#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance //BatteryLife
//#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeMsgBasedC1e
//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x2000
//#define IDSOPT_IDS_ENABLED TRUE
#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
#define BLDOPT_REMOVE_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
#define BLDCFG_PSTATE_HPC_MODE FALSE
#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap
/*
* Agesa entry points used in this implementation.
*/
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
*/
#define AGESA_ENTRY_INIT_RESET TRUE//FALSE
#define AGESA_ENTRY_INIT_RECOVERY FALSE
#define AGESA_ENTRY_INIT_EARLY TRUE
#define AGESA_ENTRY_INIT_POST TRUE
#define AGESA_ENTRY_INIT_ENV TRUE
#define AGESA_ENTRY_INIT_MID TRUE
#define AGESA_ENTRY_INIT_LATE TRUE
#define AGESA_ENTRY_INIT_S3SAVE TRUE
#define AGESA_ENTRY_INIT_RESUME TRUE
#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
/*****************************************************************************
* Define the RELEASE VERSION string
*
* The Release Version string should identify the next planned release.
* When a branch is made in preparation for a release, the release manager
* should change/confirm that the branch version of this file contains the
* string matching the desired version for the release. The trunk version of
* the file should always contain a trailing 'X'. This will make sure that a
* development build from trunk will not be confused for a released version.
* The release manager will need to remove the trailing 'X' and update the
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
// This is the delivery package title, "MarG34PI"
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '9', '.', '0', ' ', ' ', ' ', ' '}
// The Maranello solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the G34 socket.
#define INSTALL_G34_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_10_SUPPORT TRUE
#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT TRUE
#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT
#if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE
#undef INSTALL_FAMILY_10_SUPPORT
#define INSTALL_FAMILY_10_SUPPORT FALSE
#endif
#endif
#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT
#if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE
#undef INSTALL_FAMILY_15_MODEL_0x_SUPPORT
#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT FALSE
#endif
#endif
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0xFF)
#define DFLT_SCRUB_L2_RATE (0x10)
#define DFLT_SCRUB_L3_RATE (0x10)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0x12)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
#define DFLT_VRM_SLEW_RATE (2500)
/* Process the options...
* This file include MUST occur
AFTER the user option selection settings
*/
CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] =
{
HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
0, 0,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF
};
#define BLDCFG_BUID_SWAP_LIST &MaranelloManualBuidSwapList
// And another platform specific one ...
//CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[2] =
//{
// HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
// HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M,
// HT_LIST_TERMINAL
//};
CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[] =
{
HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M,
HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK,
HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M,
HT_LIST_TERMINAL
};
#define BLDCFG_HTFABRIC_LIMITS_LIST &MaranelloCpuToCpuLimitList
// A performance-per-watt optimization.
CONST SKIP_REGANG ROMDATA PerfPerWatt[] = {
HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, POWERED_OFF,
HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, POWERED_OFF,
HT_LIST_TERMINAL,
};
// uncomment the line below to make Perf-per-watt enabled by default.
#define BLDCFG_LINK_SKIP_REGANG_LIST &PerfPerWatt
CONST IO_PCB_LIMITS ROMDATA MaranelloIoLimitList[2] =
{
HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M,
HT_LIST_TERMINAL
};
#define BLDCFG_HTCHAIN_LIMITS_LIST &MaranelloIoLimitList
CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA DinarPhysicalSocketMap[] =
{
// Source Socket, Link (4-7 are sublink 1), Target Socket
{0, 0, 1},
{0, 1, 1},
{0, 3, 1},
{0, 4, 1},
{0, 5, 1},
{0, 7, 1},
};
#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP &DinarPhysicalSocketMap
/*
* PCI Bus numbers for Drachma/Peso board
*/
CONST OVERRIDE_BUS_NUMBERS ROMDATA MaranelloOverrideBusNumbers[5] =
{
// Socket, Link, SecBus, SubBus
0, 2, 0x00, 0xBF, // RD890 of Dinar
1, 0, 0xC0, 0xFF, // HTX
HT_LIST_TERMINAL
};
#define BLDCFG_BUS_NUMBERS_LIST &MaranelloOverrideBusNumbers
CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA DinarDeemphasisList[] =
{
{ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_200M, HT_FREQUENCY_1800M, DeemphasisLevelNone, DcvLevelNone},
{ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2600M, DeemphasisLevelMinus3, DcvLevelMinus3},
{ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2800M, HT_FREQUENCY_MAX, DeemphasisLevelMinus6, DcvLevelMinus6},
0xFF
};
#define BLDCFG_PLATFORM_DEEMPHASIS_LIST DinarDeemphasisList
/*
CONST SKIP_REGANG ROMDATA DinarSkipRegangMap[] =
{
// {socketA, linkA, socketB, linkB}
{0, 0, 1, 1},
};
#define BLDCFG_LINK_SKIP_REGANG_LIST &DinarSkipRegangMap
*/
/*
* Device Capabilities Override for disabling ID Clumping
*/
CONST DEVICE_CAP_OVERRIDE ROMDATA MaranelloOverrideDevCap[2] =
{
HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
0, 0, HT_LIST_MATCH_ANY, {0, 0, 0, 0, 0, 1, 0}, 0, 0, 0, 0, {0},
HT_LIST_TERMINAL
};
#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
#include "cpuFamilyTranslation.h"
#include "AdvancedApi.h"
#include "heapManager.h"
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterfaceStub.h"
#include "PlatformInstall.h"
/*----------------------------------------------------------------------------------------
* CUSTOMER OVERIDES MEMORY TABLE
*----------------------------------------------------------------------------------------
*/
/*
* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
//
// The following macros are supported (use comma to separate macros):
//
// MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
// The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
// AGESA will base on this value to disable unused MemClk to save power.
// Example:
// BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
// Bit AM3/S1g3 pin name
// 0 M[B,A]_CLK_H/L[0]
// 1 M[B,A]_CLK_H/L[1]
// 2 M[B,A]_CLK_H/L[2]
// 3 M[B,A]_CLK_H/L[3]
// 4 M[B,A]_CLK_H/L[4]
// 5 M[B,A]_CLK_H/L[5]
// 6 M[B,A]_CLK_H/L[6]
// 7 M[B,A]_CLK_H/L[7]
// And platform has the following routing:
// CS0 M[B,A]_CLK_H/L[4]
// CS1 M[B,A]_CLK_H/L[2]
// CS2 M[B,A]_CLK_H/L[3]
// CS3 M[B,A]_CLK_H/L[5]
// Then platform can specify the following macro:
// MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
//
// CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
// The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
// AGESA will base on this value to tristate unused CKE to save power.
//
// ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
// The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
// AGESA will base on this value to tristate unused ODT pins to save power.
//
// CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
// The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
// AGESA will base on this value to tristate unused Chip select to save power.
//
// NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
// Specifies the number of DIMM slots per channel.
//
// NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
// Specifies the number of channels per socket.
//
// Dinar has the following routing:
// CS0 M[B,A]_CLK_H/L[0]
// CS1 M[B,A]_CLK_H/L[2]
// CS2 M[B,A]_CLK_H/L[1]
// CS3 M[B,A]_CLK_H/L[3]
MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x01, 0x04, 0x02, 0x08, 0x00, 0x00),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
PSO_END
};
/*
* These tables are optional and may be used to adjust memory timing settings
*/
#include "mm.h"
#include "mn.h"
//HY Customer table
UINT8 AGESA_MEM_TABLE_HY[][sizeof(MEM_TABLE_ALIAS)] =
{
// Hardcoded Memory Training Values
// The following macro should be used to override training values for your platform
//
// DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
//
// NOTE:
// The following training hardcode values are example values that were taken from a tilapia motherboard
// with a particular DIMM configuration. To harcode your own values, uncomment the appropriate line in
// the table and replace the byte lane values with your own.
//
// ------------------ BYTE LANES ----------------------
// BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC
// Write Data Timing
// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
// DQS Receiver Enable
// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
// Write DQS Delays
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
// Read DQS Delays
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
//--------------------------------------------------------------------------------------------------------------------------------------------------
// TABLE END
NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
};
UINT8 SizeOfTableHy = sizeof (AGESA_MEM_TABLE_HY) / sizeof (AGESA_MEM_TABLE_HY[0]);
/* ***************************************************************************
* Optional User code to be included into the AGESA build
* These may be 32-bit call-out routines...
*/
//AGESA_STATUS
//AgesaReadSpd (
// IN UINTN FcnData,
// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
// )
//{
// /* platform code to read an SPD... */
// return Status;
//}
/* ***************************************************************************
* Optional User code to be included into the AGESA build
* These may be 32-bit call-out routines...
*/
//AGESA_STATUS
//AgesaReadSpd (
// IN UINTN FcnData,
// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
// )
//{
// /* platform code to read an SPD... */
// return Status;
//}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
extern struct chip_operations mainboard_ops;
struct mainboard_config {};

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#*****************************************************************************
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#*****************************************************************************
entries
#start-bit length config config-ID name
#0 8 r 0 seconds
#8 8 r 0 alarm_seconds
#16 8 r 0 minutes
#24 8 r 0 alarm_minutes
#32 8 r 0 hours
#40 8 r 0 alarm_hours
#48 8 r 0 day_of_week
#56 8 r 0 day_of_month
#64 8 r 0 month
#72 8 r 0 year
#80 4 r 0 rate_select
#84 3 r 0 REF_Clock
#87 1 r 0 UIP
#88 1 r 0 auto_switch_DST
#89 1 r 0 24_hour_mode
#90 1 r 0 binary_values_enable
#91 1 r 0 square-wave_out_enable
#92 1 r 0 update_finished_enable
#93 1 r 0 alarm_interrupt_enable
#94 1 r 0 periodic_interrupt_enable
#95 1 r 0 disable_clock_updates
#96 288 r 0 temporary_filler
0 384 r 0 reserved_memory
384 1 e 4 boot_option
385 1 e 4 last_boot
386 1 e 1 ECC_memory
388 4 r 0 reboot_bits
392 3 e 5 baud_rate
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
416 4 e 7 boot_first
420 4 e 7 boot_second
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
5 0 115200
5 1 57600
5 2 38400
5 3 19200
5 4 9600
5 5 4800
5 6 2400
5 7 1200
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
7 0 Network
7 1 HDD
7 2 Floppy
7 8 Fallback_Network
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums
checksum 392 983 984

104
src/mainboard/amd/dinar/devicetree.cb Normal file
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#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
chip northbridge/amd/agesa/family15/root_complex
device lapic_cluster 0 on
chip cpu/amd/agesa/family15
device lapic 0x20 on end
end
end
device pci_domain 0 on
subsystemid 0x1022 0x1705 inherit
chip northbridge/amd/agesa/family15 # CPU side of HT root complex
device pci 18.0 on end # Link 0
device pci 18.0 on # Link 1, IO-HUB on socket0 link 2(internal Node0 Link 1)
chip northbridge/amd/cimx/rd890 # North Bridge PCI side of HT Root complex
device pci 0.0 on end # HT Root Complex
device pci 0.1 off end # CLKCONFIG
device pci 2.0 on end # GPP1 Port0
device pci 3.0 off end # GPP1 Port1
device pci 4.0 off end # GPP3a Port0
device pci 5.0 off end # GPP3a Port1
device pci 6.0 off end # GPP3a Port2
device pci 7.0 off end # GPP3a Port3
device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time
device pci 9.0 off end # GPP3a Port4
device pci a.0 off end # GPP3a Port5
device pci b.0 off end # GPP2 Port0 (Not for sr5650)
device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670)
device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576
register "gpp1_configuration" = "0" # Configuration 16:0 default
register "gpp2_configuration" = "1" # Configuration 8:8
register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1
register "port_enable" = "0x2104"
end # northbridge/amd/cimx/rd890
chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pri bus
device pci 11.0 on end # SATA
device pci 12.0 on end # USB1
device pci 12.1 on end # USB1
device pci 12.2 on end # USB1
device pci 13.0 on end # USB2
device pci 13.1 on end # USB2
device pci 13.2 on end # USB2
device pci 14.0 on # SM
end # SM
device pci 14.1 off end # IDE 0x439c
device pci 14.2 off end # HDA 0x4383
device pci 14.3 on # LPC
chip superio/smsc/sch4037 # SIO SMSC SCH4037
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
irq 0x74 = 2
end
device pnp 2e.3 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
irq 0x74 = 4
end
device pnp 2e.4 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.5 on # COM2 / IR
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.7 on # PS/2 keyboard / mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1 # PS/2 keyboard interrupt
irq 0x72 = 12 # PS/2 mouse interrupt
end
end #SIO SMSC307
end #LPC
device pci 14.4 on end # PCI bridge, 0x4384
device pci 14.5 on end # USB 3
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb700
end # device pci 18.0
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
device pci 18.5 on end
end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
end #pci_domain
end #northbridge/amd/agesa/family15/root_complex

333
src/mainboard/amd/dinar/dimmSpd.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
#define SMBUS_BASE_ADDR 0xB00
#define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
#define LTC4305_SMBUS_ADDR 0x94
typedef struct _DIMM_INFO_SMBUS{
UINT8 SocketId;
UINT8 MemChannelId;
UINT8 DimmId;
UINT8 SmbusAddress;
} DIMM_INFO_SMBUS;
/*
* SPD address table - porting required
*/
STATIC CONST DIMM_INFO_SMBUS SpdAddrLookup [] =
{
/* Socket, Channel, Dimm, Smbus */
{0, 0, 0, 0xAC},
{0, 0, 1, 0xAE},
{0, 1, 0, 0xA8},
{0, 1, 1, 0xAA},
{0, 2, 0, 0xA4},
{0, 2, 1, 0xA6},
{0, 3, 0, 0xA0},
{0, 3, 1, 0xA2},
{1, 0, 0, 0xAC},
{1, 0, 1, 0xAE},
{1, 1, 0, 0xA8},
{1, 1, 1, 0xAA},
{1, 2, 0, 0xA4},
{1, 2, 1, 0xA6},
{1, 3, 0, 0xA0},
{1, 3, 1, 0xA2}
};
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
AGESA_STATUS
AmdMemoryReadSPD (
IN UINT32 Func,
IN UINT32 Data,
IN OUT AGESA_READ_SPD_PARAMS *SpdData
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/
STATIC
VOID
WritePmReg (
IN UINT8 Reg,
IN UINT8 Data
)
{
__outbyte (0xCD6, Reg);
__outbyte (0xCD7, Data);
}
STATIC
VOID
SetupFch (
IN UINT16
IN IoBase
)
{
AMD_CONFIG_PARAMS StdHeader;
UINT32 PciData32;
UINT8 PciData8;
PCI_ADDR PciAddress;
/* Set SMBUS MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90);
PciData32 = (SMBUS_BASE_ADDR & 0xFFFFFFF0) | BIT0;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader);
/* Enable SMBUS MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2);
LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ;
PciData8 |= BIT0;
LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader);
/* set SMBus clock to 400 KHz */
__outbyte (IoBase + 0x0E, 66000000 / 400000 / 4);
}
/*
*
* ReadSmbusByteData - read a single SPD byte from any offset
*
*/
STATIC
AGESA_STATUS
ReadSmbusByteData (
IN UINT16 Iobase,
IN UINT8 Address,
OUT UINT8 *ByteData,
IN UINTN Offset
)
{
UINTN Status;
UINT64 Limit;
Address |= 1; // set read bit
__outbyte (Iobase + 0, 0xFF); // clear error status
__outbyte (Iobase + 1, 0x1F); // clear error status
__outbyte (Iobase + 3, Offset); // offset in eeprom
__outbyte (Iobase + 4, Address); // slave address and read bit
__outbyte (Iobase + 2, 0x48); // read byte command
/* time limit to avoid hanging for unexpected error status (should never happen) */
Limit = __rdtsc () + 2000000000 / 10;
for (;;) {
Status = __inbyte (Iobase);
if (__rdtsc () > Limit) break;
if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
if ((Status & 1) == 1) continue; // HostBusy set, keep waiting
break;
}
*ByteData = __inbyte (Iobase + 5);
if (Status == 2) Status = 0; // check for done with no errors
return Status;
}
/*
*
* WriteSmbusByteData - Write a single SPD byte onto any offset
*
*/
STATIC
AGESA_STATUS
WriteSmbusByteData (
IN UINT16 Iobase,
IN UINT8 Address,
IN UINT8 ByteData,
IN UINTN Offset
)
{
UINTN Status;
UINT64 Limit;
Address &= 0xFE; // set write bit
__outbyte (Iobase + 0, 0xFF); // clear error status
__outbyte (Iobase + 1, 0x1F); // clear error status
__outbyte (Iobase + 3, Offset); // offset in eeprom
__outbyte (Iobase + 4, Address); // slave address and write bit
__outbyte (Iobase + 5, ByteData); // offset in byte data //
__outbyte (Iobase + 2, 0x48); // write byte command
/* time limit to avoid hanging for unexpected error status (should never happen) */
Limit = __rdtsc () + 2000000000 / 10;
for (;;) {
Status = __inbyte (Iobase);
if (__rdtsc () > Limit) break;
if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
if ((Status & 1) == 1) continue; // HostBusy set, keep waiting
break;
}
if (Status == 2) Status = 0; // check for done with no errors
return Status;
}
/*
*
* ReadSmbusByte - read a single SPD byte from the default offset
* this function is faster function readSmbusByteData
*
*/
STATIC
AGESA_STATUS
ReadSmbusByte (
IN UINT16 Iobase,
IN UINT8 Address,
OUT UINT8 *Buffer
)
{
UINTN Status;
UINT64 Limit;
__outbyte (Iobase + 0, 0xFF); // clear error status
__outbyte (Iobase + 1, 0x1F); // clear error status
__outbyte (Iobase + 2, 0x44); // read command
// time limit to avoid hanging for unexpected error status
Limit = __rdtsc () + 2000000000 / 10;
for (;;) {
Status = __inbyte (Iobase);
if (__rdtsc () > Limit) break;
if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
if ((Status & 1) == 1) continue; // HostBusy set, keep waiting
break;
}
Buffer [0] = __inbyte (Iobase + 5);
if (Status == 2) Status = 0; // check for done with no errors
return Status;
}
/*
*
* ReadSpd - Read one or more SPD bytes from a DIMM.
* Start with offset zero and read sequentially.
* Optimization relies on autoincrement to avoid
* sending offset for every byte.
* Reads 128 bytes in 7-8 ms at 400 KHz.
*
*/
STATIC
AGESA_STATUS
ReadSpd (
IN UINT16 IoBase,
IN UINT8 SmbusSlaveAddress,
OUT UINT8 *Buffer,
IN UINTN Count
)
{
UINTN Index, Status;
/* read the first byte using offset zero */
Status = ReadSmbusByteData (IoBase, SmbusSlaveAddress, Buffer, 0);
if (Status) return Status;
/* read the remaining bytes using auto-increment for speed */
for (Index = 1; Index < Count; Index++){
Status = ReadSmbusByte (IoBase, SmbusSlaveAddress, &Buffer [Index]);
if (Status) return Status;
}
return 0;
}
AGESA_STATUS
AmdMemoryReadSPD (
IN UINT32 Func,
IN UINT32 Data,
IN OUT AGESA_READ_SPD_PARAMS *SpdData
)
{
AGESA_STATUS Status;
UINT8 SmBusAddress = 0;
UINTN Index;
UINTN MaxSocket = DIMENSION (SpdAddrLookup);
for (Index = 0; Index < MaxSocket; Index ++){
if ((SpdData->SocketId == SpdAddrLookup[Index].SocketId) &&
(SpdData->MemChannelId == SpdAddrLookup[Index].MemChannelId) &&
(SpdData->DimmId == SpdAddrLookup[Index].DimmId)) {
SmBusAddress = SpdAddrLookup[Index].SmbusAddress;
break;
}
}
if (SmBusAddress == 0) return AGESA_ERROR;
SetupFch (SMBUS_BASE_ADDR);
Status = WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x80, 0x03);
switch (SpdData->SocketId) {
case 0:
/* Switch onto the First CPU Socket SMBUS */
WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x80, 0x03);
break;
case 1:
/* Switch onto the Second CPU Socket SMBUS */
WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x40, 0x03);
break;
default:
/* Switch off two CPU Sockets SMBUS */
WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x00, 0x03);
break;
}
Status = ReadSpd (SMBUS_BASE_ADDR, SmBusAddress, SpdData->Buffer, 256);
/*Output SPD Debug Message*/
printk(BIOS_EMERG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__);
printk(BIOS_DEBUG, " Status = %d\n",Status);
printk(BIOS_DEBUG, "SocketId MemChannelId SpdData->DimmId SmBusAddress Buffer\n");
printk(BIOS_DEBUG, "%x, %x, %x, %x, %x\n", SpdData->SocketId, SpdData->MemChannelId, SpdData->DimmId, SmBusAddress, SpdData->Buffer);
/* Switch off two CPU Sockets SMBUS */
WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x00, 0x03);
return Status;
}

1148
src/mainboard/amd/dinar/dsdt.asl Normal file
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173
src/mainboard/amd/dinar/fadt.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
* ACPI - create the Fixed ACPI Description Tables (FADT)
*/
#include <string.h>
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <device/device.h>
#include "Platform.h" /*sb700 platform header*/
#ifndef ACPI_BLK_BASE
#define ACPI_BLK_BASE PM1_EVT_BLK_ADDRESS
#endif
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
/* Prepare the header */
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
header->length = 244;
header->revision = 1;
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id, ASLC, 4);
header->asl_compiler_revision = 0;
fadt->firmware_ctrl = (u32) facs;
fadt->dsdt = (u32) dsdt;
/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
fadt->preferred_pm_profile = 0x03;
fadt->sci_int = 9;
/* disable system management mode by setting to 0: */
fadt->smi_cmd = 0;
fadt->acpi_enable = 0xf0;
fadt->acpi_disable = 0xf1;
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0xe2;
/* RTC_En_En, TMR_En_En, GBL_EN_EN */
outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */
fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
fadt->pm1b_evt_blk = 0x0000;
fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
fadt->pm1b_cnt_blk = 0x0000;
fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
fadt->gpe0_blk = GPE0_BLK_ADDRESS;
fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 8;
fadt->gpe1_blk_len = 0;
fadt->gpe1_base = 0;
fadt->cst_cnt = 0xe3;
fadt->p_lvl2_lat = 101;
fadt->p_lvl3_lat = 1001;
fadt->flush_size = 0;
fadt->flush_stride = 0;
fadt->duty_offset = 1;
fadt->duty_width = 3;
fadt->day_alrm = 0; /* 0x7d these have to be */
fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
fadt->century = 0; /* 0x7f to make rtc alrm work */
fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
fadt->flags = 0x0001c1a5;/* 0x25; */
fadt->res2 = 0;
fadt->reset_reg.space_id = 1;
fadt->reset_reg.bit_width = 8;
fadt->reset_reg.bit_offset = 0;
fadt->reset_reg.resv = 0;
fadt->reset_reg.addrl = 0xcf9;
fadt->reset_reg.addrh = 0x0;
fadt->reset_value = 6;
fadt->x_firmware_ctl_l = (u32) facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (u32) dsdt;
fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = 1;
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 1;
fadt->x_pm1b_evt_blk.bit_width = 4;
fadt->x_pm1b_evt_blk.bit_offset = 0;
fadt->x_pm1b_evt_blk.resv = 0;
fadt->x_pm1b_evt_blk.addrl = 0x0;
fadt->x_pm1b_evt_blk.addrh = 0x0;
fadt->x_pm1a_cnt_blk.space_id = 1;
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 1;
fadt->x_pm1b_cnt_blk.bit_width = 2;
fadt->x_pm1b_cnt_blk.bit_offset = 0;
fadt->x_pm1b_cnt_blk.resv = 0;
fadt->x_pm1b_cnt_blk.addrl = 0x0;
fadt->x_pm1b_cnt_blk.addrh = 0x0;
fadt->x_pm2_cnt_blk.space_id = 1;
fadt->x_pm2_cnt_blk.bit_width = 0;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = 1;
fadt->x_gpe0_blk.bit_width = 32;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;
fadt->x_gpe1_blk.bit_width = 0;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.resv = 0;
fadt->x_gpe1_blk.addrl = 0;
fadt->x_gpe1_blk.addrh = 0x0;
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
}

156
src/mainboard/amd/dinar/get_bus_conf.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
#include <cpu/amd/amdfam15.h>
#include "agesawrapper.h"
#if CONFIG_AMD_SB_CIMX
#include <sb_cimx.h>
#endif
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
u8 bus_isa;
u8 bus_sb700[2];
u8 bus_rd890[14];
/*
* Here you only need to set value in pci1234 for HT-IO that could be installed or not
* You may need to preset pci1234 for HTIO board,
* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
*/
u32 pci1234x[] = {
0x0000ff0,
};
/*
* HT Chain device num, actually it is unit id base of every ht device in chain,
* assume every chain only have 4 ht device at most
*/
u32 hcdnx[] = {
0x20202020,
};
u32 bus_type[256];
u32 sbdn_sb700;
u32 sbdn_rd890;
static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 status;
device_t dev;
int i, j;
if (get_bus_conf_done == 1)
return; /* do it only once */
get_bus_conf_done = 1;
printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n");
/*
* This is the call to AmdInitLate. It is really in the wrong place, conceptually,
* but functionally within the coreboot model, this is the best place to make the
* call. The logically correct place to call AmdInitLate is after PCI scan is done,
* after the decision about S3 resume is made, and before the system tables are
* written into RAM. The routine that is responsible for writing the tables is
* "write_tables", called near the end of "hardwaremain". There is no platform
* specific entry point between the S3 resume decision point and the call to
* "write_tables", and the next platform specific entry points are the calls to
* the ACPI table write functions. The first of ose would seem to be the right
* place, but other table write functions, e.g. the PIRQ table write function, are
* called before the ACPI tables are written. This routine is called at the beginning
* of each of the write functions called prior to the ACPI write functions, so this
* becomes the best place for this call.
*/
status = agesawrapper_amdinitlate();
if(status) {
printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
}
printk(BIOS_DEBUG, "Got past agesawrapper_amdinitlate\n");
sbdn_sb700 = 0;
for (i = 0; i < ARRAY_SIZE(bus_sb700); i++) {
bus_sb700[i] = 0;
}
for (i = 0; i < ARRAY_SIZE(bus_rd890); i++) {
bus_rd890[i] = 0;
}
for (i = 0; i < 256; i++) {
bus_type[i] = 0; /* default ISA bus. */
}
bus_type[0] = 1; /* pci */
bus_rd890[0] = (pci1234x[0] >> 16) & 0xff;
bus_sb700[0] = bus_rd890[0];
/* sb700 */
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
if (dev) {
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
for (j = bus_sb700[1]; j < bus_isa; j++)
bus_type[j] = 1;
}
/* rd890 */
for (i = 1; i < ARRAY_SIZE(bus_rd890); i++) {
dev = dev_find_slot(bus_rd890[0], PCI_DEVFN(sbdn_rd890 + i, 0));
if (dev) {
bus_rd890[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
if(255 != bus_rd890[i]) {
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
bus_type[bus_rd890[i]] = 1; /* PCI bus. */
}
}
}
/* I/O APICs: APIC ID Version State Address */
bus_isa = 10;
#if CONFIG_AMD_SB_CIMX
// sb_After_Pci_Init();
// sb_Late_Post();
#endif
printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - End.\n");
}

482
src/mainboard/amd/dinar/gpio.c Normal file
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@ -0,0 +1,482 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "Filecode.h"
#include "Hudson-2.h"
#include "AmdSbLib.h"
#include "gpio.h"
#define FILECODE UNASSIGNED_FILE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
#ifndef SB_GPIO_REG01
#define SB_GPIO_REG01 1
#endif
#ifndef SB_GPIO_REG07
#define SB_GPIO_REG07 7
#endif
#ifndef SB_GPIO_REG25
#define SB_GPIO_REG25 25
#endif
#ifndef SB_GPIO_REG26
#define SB_GPIO_REG26 26
#endif
#ifndef SB_GPIO_REG27
#define SB_GPIO_REG27 27
#endif
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
void gpioEarlyInit (void);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/
void
gpioEarlyInit(
void
)
{
u8 Flags;
u8 Data8 = 0;
u8 StripInfo = 0;
u8 BoardType = 1;
u8 RegIndex8 = 0;
u8 boardRevC = 0x2;
u16 Data16 = 0;
u32 Index = 0;
u32 AcpiMmioAddr = 0;
u32 GpioMmioAddr = 0;
u32 IoMuxMmioAddr = 0;
u32 MiscMmioAddr = 0;
u32 SmiMmioAddr = 0;
u32 andMask32 = 0;
// Enable HUDSON MMIO Base (AcpiMmioAddr)
ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
Data8 |= BIT0;
WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
// Get HUDSON MMIO Base (AcpiMmioAddr)
ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8);
Data16 = Data8 << 8;
ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8);
Data16 |= Data8;
AcpiMmioAddr = (u32)Data16 << 16;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
IoMuxMmioAddr = AcpiMmioAddr + IOMUX_BASE;
MiscMmioAddr = AcpiMmioAddr + MISC_BASE;
Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80);
if ((Data8 & BIT4) == 0) {
BoardType = 0; // external clock board
}
Data8 = Mmio8_G (GpioMmioAddr, GPIO_30);
StripInfo = (Data8 & BIT7) >> 7;
Data8 = Mmio8_G (GpioMmioAddr, GPIO_31);
StripInfo |= (Data8 & BIT7) >> 6;
if (StripInfo < boardRevC) { // for old board. Rev B
Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3
Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0
}
for (Index = 0; Index < MAX_GPIO_NO; Index++) {
if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) {
if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) {
// Configure multi-funtion
Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio));
}
// Configure GPIO
if(!((gpio_table[Index].NonGpioGevent & NonGpio))) {
Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type);
Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value);
}
if (Index == GPIO_65) {
if ( BoardType == 0 ) {
Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3
}
}
}
// Configure GEVENT
if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) {
SmiMmioAddr = AcpiMmioAddr + SMI_BASE;
andMask32 = ~(1 << (Index - GEVENT_00));
//EventEnable: 0-Disable, 1-Enable
Mmio32_And_Or (SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00)));
//SciTrig: 0-Falling Edge, 1-Rising Edge
Mmio32_And_Or (SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00)));
//SciLevl: 0-Edge trigger, 1-Level Trigger
Mmio32_And_Or (SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00)));
//SmiSciEn: 0-Not send SMI, 1-Send SMI
Mmio32_And_Or (SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00)));
//SciS0En: 0-Disable, 1-Enable
Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00)));
//SciMap: 00000b ~ 11111b
RegIndex8=(u8)((Index - GEVENT_00) >> 2);
Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8);
Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8));
//SmiTrig: 0-Active Low, 1-Active High
Mmio32_And_Or (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)));
//SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13
RegIndex8=(u8)((Index - GEVENT_00) >> 4);
Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2);
Mmio32_And_Or (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8));
}
}
//
// config MXM
// GPIO9: Input for MXM_PRESENT2#
// GPIO10: Input for MXM_PRESENT1#
// GPIO28: Input for MXM_PWRGD
// GPIO35: Output for MXM Reset
// GPIO45: Output for MXM Power Enable, active HIGH
// GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable
// GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO
//
// set INTE#/GPIO32 as GPO for PCIE_SW
RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); // GPIO
RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO
RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6);
// set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN
RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); // GPIO
RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); // GPO
// set AD9/GPIO9 as GPI for MXM_PRESENT2#
RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); // GPIO
RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); // GPI
// set AD10/GPIO10 as GPI for MXM_PRESENT1#
RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); // GPIO
RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); // GPI
// set GNT1#/GPIO44 as GPO for MXM Reset
RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); // GPIO
RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); // GPO
// set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable
RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); // GPIO
RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); // GPO
// set AD28/GPIO28 as GPI for MXM_PWRGD
RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO
RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI
// set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=0 (Output LOW)
RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3);
RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3);
RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3);
RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x23, BIT3);
RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x23, BIT3);
RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x23, BIT3);
//
// [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default).
//
//Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20));
//Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20)));
// check if there any GFX card
Flags = 0;
// Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL);
// Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09);
ReadMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, &Data8);
if (!(Data8 & BIT7))
{
//Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG10);
ReadMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, &Data8);
if (!(Data8 & BIT7))
{
Flags = 1;
}
}
if ( Flags )
{
// [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467
RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0);
// [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6);
//PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
SbStall (10000);
// Write the GPIO55(MXM_PWR_EN) to enable the integrated power module
RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6);
//PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
// WAIT POWER READY: GPIO28 (MXM_PWRGD)
//while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){}
ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
while (!(Data8 && BIT7))
{
ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
}
// [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset
// RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6);
}
else
{
// Write the GPIO55(MXM_PWR_EN) to disable the integrated power module
RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xBF, 0);
//PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
SbStall (10000);
// [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down
RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0);
}
//
// APU GPP0: On board LAN
// GPIO25: PCIE_RST#_LAN, LOW active
// GPIO63: LAN_CLKREQ#
// GPIO197: LOM_POWER, HIGH Active
// Clock: GPP_CLK3
//
// Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER
RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); // GPIO
// RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0); // GPO
RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH
RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN:
RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO
// RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO
RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH
RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ#
RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3#
RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3
//
// APU GPP1: WUSB
// GPIO1: MPCIE_RST2#, LOW active
// GPIO13: WU_DISABLE#, LOW active
// GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default)
//
// Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable
RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); // GPIO
// RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // GPO
RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // output LOW
RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// Setup AD01/GPIO01 as GPO for MPCIE_RST2#
RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); // GPIO
// RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0); // GPO
RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); // output LOW
RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB
// RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1); // GPIO
// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0); // GPO
// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6); // output HIGH
// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
//
// APU GPP2: WWAN
// GPIO0: MPCIE_RST1#, LOW active
// GPIO14: WP_DISABLE#, LOW active
// GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default)
//
// Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable
RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); // GPIO
// RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // GPO
RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // output LOW
RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// Set AD00/GPIO00 as GPO for MPCIE_RST1#
RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); // GPIO
// RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0); // GPO
// RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6); // output LOW
RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN
// RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1); // GPIO
// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0); // GPO
// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6);
// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3);
//
// APU GPP3: 1394
// GPIO59: Power control, HIGH active
// GPIO27: PCIE_RST#_1394, LOW active
// GPIO41: CLKREQ#
// Clock: GPP_CLK8
//
// Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON:
RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO
// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO
RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH
RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394
RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); // GPIO
// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0); // GPO
RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // output HIGH
RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ#
RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); // CLK_REQ2#
// set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C
RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); // GPIO
RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); // GPO
RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); // output HIGH
RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// To fix glitch issue
RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW
//
// Enable/Disable OnBoard LAN
//
if (!CONFIG_ONBOARD_LAN)
{ // 1 - DISABLED
RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off
RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0);
RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); // PULL UP - DISABLED
RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); // Disable GPP_CLK3
}
// else
// { // 0 - AUTO
// // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable)
// RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3);
// RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3);
// }
//
// Enable/Disable 1394
//
if (!CONFIG_ONBOARD_1394)
{ // 1 - DISABLED
// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW
RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off
RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0);
RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); // pullup DISABLE
RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); // DISABLE GPP_CLK8
// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6); // set GPIO_GATE_C to HIGH
}
// else
// { // 0 - AUTO
// // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH)
// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6);
// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);
//
// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6);
// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3);
// }
//
// external USB 3.0 control:
// amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE
// GPIO26: PCIE_RST#_USB3.0
// GPIO46: PCIE_USB30_CLKREQ#
// GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON
// Clock: GPP_CLK7
// GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
// if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) {
// disable Onboard NEC USB3.0 controller
if (!CONFIG_ONBOARD_USB30) {
RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0);
RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0);
RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE
RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); // DISABLE GPP_CLK7
RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
}
// }
//
// BlueTooth control: BT_ON
// amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE
// GPIO07: BT_ON, 0 - OFF, 1 - ON
//
if (!CONFIG_ONBOARD_BLUETOOTH) {
//- if (SystemConfiguration.amdBlueTooth == 1) {
RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0);
//- }
}
//
// WebCam control:
// amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE
// GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF
//
if (!CONFIG_ONBOARD_WEBCAM) {
//- if (SystemConfiguration.amdWebCam == 1) {
RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6);
//- }
}
//
// Travis enable:
// amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE
// GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE
//
if (!CONFIG_ONBOARD_TRAVIS) {
//- if (SystemConfiguration.amdTravisCtrl == 0) {
RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6);
//- }
}
//
// Disable Light Sensor if needed
//
if (CONFIG_ONBOARD_LIGHTSENSOR) {
//- if (SystemConfiguration.amdLightSensor == 1) {
RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1);
//- }
}
}

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src/mainboard/amd/dinar/irq_tables.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
#include <arch/pirq_routing.h>
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
u8 slot, u8 rfu)
{
pirq_info->bus = bus;
pirq_info->devfn = devfn;
pirq_info->irq[0].link = link0;
pirq_info->irq[0].bitmap = bitmap0;
pirq_info->irq[1].link = link1;
pirq_info->irq[1].bitmap = bitmap1;
pirq_info->irq[2].link = link2;
pirq_info->irq[2].bitmap = bitmap2;
pirq_info->irq[3].link = link3;
pirq_info->irq[3].bitmap = bitmap3;
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
extern u8 bus_isa;
extern u8 bus_sb700[2];
extern unsigned long sbdn_sb700;
unsigned long write_pirq_routing_table(unsigned long addr)
{
struct irq_routing_table *pirq;
struct irq_info *pirq_info;
u32 slot_num;
u8 *v;
u8 sum = 0;
int i;
get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
/* Align the table to be 16 byte aligned. */
addr += 15;
addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (u8 *) (addr);
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_sb700[0];
pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4;
pirq->exclusive_irqs = 0;
pirq->rtr_vendor = 0x1002;
pirq->rtr_device = 0x4384;
pirq->miniport_data = 0;
memset(pirq->rfu, 0, sizeof(pirq->rfu));
pirq_info = (void *)(&pirq->checksum + 1);
slot_num = 0;
/* pci bridge */
write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4,
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0);
pirq_info++;
slot_num++;
pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++)
sum += v[i];
sum = pirq->checksum - sum;
if (sum != pirq->checksum) {
pirq->checksum = sum;
}
printk(BIOS_INFO, "write_pirq_routing_table done.\n");
return (unsigned long)pirq_info;
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
#include <boot/tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <NbPlatform.h>
#include "chip.h"
#define ONE_MB 0x100000
//#define SMBUS_IO_BASE 0x6000
void set_pcie_reset(void *nbconfig);
void set_pcie_dereset(void *nbconfig);
/**
* TODO
* SB CIMx callback
*/
void set_pcie_reset(void *nbconfig)
{
}
/**
* Mainboard specific RD890 CIMx callback
* Release Resets to PCIe Links
* SR5690 PCIE_RESET_GPIO1,2,3,4 to reset pcie
*/
void set_pcie_dereset(void *nbconfig)
{
//u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
u32 i;
u32 val;
u32 nb_addr;
val = 0x00000007UL;
AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig;
for (i = 0; i < MAX_NB_COUNT; i ++) {
nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX;
LibNbPciIndexRMW(nb_addr,
NB_HTIU_REGA8,
AccessS3SaveWidth32,
~val,
val,
&(pConfig->Northbridges[i]));
}
}
uint64_t uma_memory_base, uma_memory_size;
/*************************************************
* enable the dedicated function in dinar board.
*************************************************/
static void dinar_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1)
msr_t msr, msr2;
uint32_t sys_mem;
/* TOP_MEM: the top of DRAM below 4G */
msr = rdmsr(TOP_MEM);
printk
(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
__func__, msr.lo, msr.hi);
/* TOP_MEM2: the top of DRAM above 4G */
msr2 = rdmsr(TOP_MEM2);
printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
__func__, msr2.lo, msr2.hi);
/* refer to UMA Size Consideration in Family15h BKDG. */
/* Please reference MemNGetUmaSizeOR () */
/*
* Total system memory UMASize
* >= 2G 512M
* >=1G 256M
* <1G 64M
*/
sys_mem = msr.lo + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size
if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 * ONE_MB)) {
uma_memory_size = 512 * ONE_MB;
} else if (sys_mem >= 1024 * ONE_MB) {
uma_memory_size = 256 * ONE_MB;
} else {
uma_memory_size = 64 * ONE_MB;
}
uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
__func__, uma_memory_size, uma_memory_base);
/* TODO: TOP_MEM2 */
#else
uma_memory_size = 256 * ONE_MB; /* 256M recommended UMA */
uma_memory_base = 768 * ONE_MB; /* 1GB system memory supported */
#endif
}
int add_mainboard_resources(struct lb_memory *mem)
{
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
#if (CONFIG_GFXUMA == 1)
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
uma_memory_size);
#endif
return 0;
}
struct chip_operations mainboard_ops = {
CHIP_NAME("AMD DINAR Mainboard")
.enable_dev = dinar_enable,
};

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
#include <string.h>
#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
extern u8 bus_rd890[14];
extern u8 bus_sb700[2];
extern u32 bus_type[256];
extern u32 sbdn_rd890;
extern u32 sbdn_sb700;
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
u32 apicid_sb700;
u32 apicid_rd890;
device_t dev;
u32 dword;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
mptable_write_buses(mc, NULL, &bus_isa);
/*
* AGESA v5 Apply apic enumeration rules
* For systems with >= 16 APICs, put the IO-APICs at 0..n and
* put the local-APICs at m..z
* For systems with < 16 APICs, put the Local-APICs at 0..n and
* put the IO-APICs at (n + 1)..z
*/
#if CONFIG_MAX_CPUS >= 16
apicid_sb700 = 0x0;
#else
apicid_sb700 = CONFIG_MAX_CPUS + 1
#endif
apicid_rd890 = apicid_sb700 + 1;
//bus_sb700[0], TODO: why bus_sb700[0] use same value of bus_rd890[0] assigned by get_pci1234(), instead of 0.
dev = dev_find_slot(0, PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
/* Set sb700 IOAPIC ID */
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
smp_write_ioapic(mc, apicid_sb700, 0x20, dword);
/*
* 00:12.0: PROG SATA : INT F
* 00:13.0: INTA USB_0
* 00:13.1: INTB USB_1
* 00:13.2: INTC USB_2
* 00:13.3: INTD USB_3
* 00:13.4: INTC USB_4
* 00:13.5: INTD USB2
* 00:14.1: INTA IDE
* 00:14.2: Prog HDA : INT E
* 00:14.5: INTB ACI
* 00:14.6: INTB MCI
*/
/* Set RS5650 IOAPIC ID */
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (dev) {
pci_write_config32(dev, 0xF8, 0x1);
dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
smp_write_ioapic(mc, apicid_rd890, 0x20, dword);
}
}
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb700, (pin))
/* SMBUS */
//PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0
/* HD Audio */
PCI_INT(0x0, 0x14, 0x2, 0x10);
/* USB */
/* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */
/* EHCI hard-wired to 02h, corresponding to using INTB# */
/* USB1 */
PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */
PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */
PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */
/* USB2 */
PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */
PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */
PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */
/* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */
PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */
/* SATA */
PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
/* on board NIC & Slot PCIE. */
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rd890[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rd890[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rd890[0x7], 0x0, 0x0, 0x13);
*/
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_rd890, 28); /* dev d */
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_rd890[13], (((0)<<2)|(1)), apicid_rd890, 0); /* card behind dev13 */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

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src/mainboard/amd/dinar/platform_cfg.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _PLATFORM_CFG_H_
#define _PLATFORM_CFG_H_
/* northbridge customize options */
/**
* Max number of northbridges in the system
*/
#define MAX_NB_COUNT 1 //TODO: only 1 NB tested
/**
* Enable check for PCIe endpoint to be ready for PCI enumeration.
*
*/
//#define EPREADY_WORKAROUND_DISABLED
/**
* Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table.
*
*/
#define IOMMU_SUPPORT_DISABLE //TODO: enable it
/**
* Disable server PCIe hotplug support.
*/
//#define HOTPLUG_SUPPORT_DISABLED
/**
* Disable support for device number remapping for PCIe portsserver PCIe hotplug support.
*/
//#define DEVICE_REMAP_DISABLE
#endif //_PLATFORM_CFG_H_

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "NbPlatform.h"
#include "rd890_cfg.h"
#include "northbridge/amd/cimx/rd890/chip.h"
#include "nbInitializer.h"
#include <string.h>
#include <arch/ioapic.h>
#ifndef __PRE_RAM__
#include <device/device.h>
extern void set_pcie_reset(void *config);
extern void set_pcie_dereset(void *config);
/**
* Platform dependent configuration at ramstage
*/
static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr)
{
u16 i;
PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig;
//AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr);
struct northbridge_amd_cimx_rd890_config *rd890_info = NULL;
DEFAULT_PLATFORM_CONFIG(platform_config);
/* update the platform depentent configuration by devicetree */
rd890_info = nb_dev->chip_info;
platform_config.PortEnableMap = rd890_info->port_enable;
if (rd890_info->gpp1_configuration == 0) {
platform_config.Gpp1Config = GFX_CONFIG_AAAA;
} else if (rd890_info->gpp1_configuration == 1) {
platform_config.Gpp1Config = GFX_CONFIG_AABB;
}
if (rd890_info->gpp2_configuration == 0) {
platform_config.Gpp2Config = GFX_CONFIG_AAAA;
} else if (rd890_info->gpp2_configuration == 1) {
platform_config.Gpp2Config = GFX_CONFIG_AABB;
}
platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration;
if (platform_config.Gpp1Config != 0) {
pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config;
}
if (platform_config.Gpp2Config != 0) {
pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config;
}
if (platform_config.Gpp3aConfig != 0) {
pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig;
}
pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20);
for (i = 0; i <= MAX_CORE_ID; i++) {
NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF;
NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF;
}
for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2;
}
for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
if ((platform_config.PortEnableMap & (1 << i)) != 0) {
pPcieConfig->PortConfiguration[i].PortPresent = ON;
if ((platform_config.PortGen1Map & (1 << i)) != 0) {
pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1;
}
if ((platform_config.PortHotplugMap & (1 << i)) != 0) {
u16 j;
pPcieConfig->PortConfiguration[j].PortHotplug = ON; /* Enable Hotplug */
/* Set Hotplug descriptor info */
for (j = 0; j < 8; j++) {
u32 PortDescriptor;
PortDescriptor = platform_config.PortHotplugDescriptors[j];
if ((PortDescriptor & 0xF) == j) {
pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap = (PortDescriptor >> 4) & 3;
pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6) & 1;
break;
}
}
}
}
}
}
#endif // __PRE_RAM__
/**
* @brief Entry point of Northbridge CIMx callout/CallBack
*
* prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr);
*
* @param[in] u32 func Northbridge CIMx CallBackId
* @param[in] u32 data Northbridge Input Data.
* @param[in] AMD_NB_CONFIG *config Northbridge configuration structure pointer.
*
*/
static u32 rd890_callout_entry(u32 func, u32 data, void *config)
{
u32 ret = 0;
#ifndef __PRE_RAM__
device_t nb_dev = (device_t)data;
#endif
AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config;
switch (func) {
case PHCB_AmdPortTrainingCompleted:
break;
case PHCB_AmdPortResetDeassert:
#ifndef __PRE_RAM__
set_pcie_dereset(config);
#endif
break;
case PHCB_AmdPortResetAssert:
#ifndef __PRE_RAM__
set_pcie_reset(config);
#endif
break;
case PHCB_AmdPortResetSupported:
break;
case PHCB_AmdGeneratePciReset:
break;
case PHCB_AmdGetExclusionTable:
break;
case PHCB_AmdAllocateBuffer:
break;
case PHCB_AmdUpdateApicInterruptMapping:
break;
case PHCB_AmdFreeBuffer:
break;
case PHCB_AmdLocateBuffer:
break;
case PHCB_AmdReportEvent:
break;
case PHCB_AmdPcieAsmpInfo:
break;
case CB_AmdSetNbPorConfig:
break;
case CB_AmdSetHtConfig:
/*TODO: different HT path and deempasis for each NB */
nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES;
break;
case CB_AmdSetPcieEarlyConfig:
#ifndef __PRE_RAM__
nb_platform_config(nb_dev, nbConfigPtr);
#endif
break;
case CB_AmdSetEarlyPostConfig:
break;
case CB_AmdSetMidPostConfig:
nbConfigPtr->pNbConfig->IoApicBaseAddress = RD890_IOAPIC_ADDR;
#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu
/* SBIOS must alloc 16K memory for IOMMU MMIO */
UINT32 MmcfgBarAddress; //using default IOmmuBaseAddress
LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C,
AccessWidth32,
&MmcfgBarAddress,
nbConfigPtr);
MmcfgBarAddress &= ~0xf;
if (MmcfgBarAddress != 0) {
nbConfigPtr->IommuBaseAddress = MmcfgBarAddress;
}
nbConfigPtr->IommuBaseAddress = 0; //disable iommu
#endif
break;
case CB_AmdSetLatePostConfig:
break;
case CB_AmdSetRecoveryConfig:
break;
}
return ret;
}
/**
* @brief North Bridge CIMx configuration
*
* should be called before exeucte CIMx function.
* this function will be called in romstage and ramstage.
*/
void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig)
{
u16 i = 0;
PCI_ADDR PciAddress;
u32 val, sbNode, sbLink;
if (!pConfig) {
return;
}
memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK));
for (i = 0; i < MAX_NB_COUNT; i++) {
pConfig->Northbridges[i].pNbConfig = &nbConfig[i];
pConfig->Northbridges[i].pHtConfig = &htConfig[i];
pConfig->Northbridges[i].pPcieConfig = &pcieConfig[i];
pConfig->Northbridges[i].ConfigPtr = &pConfig;
}
/* Initialize all NB structures */
AmdInitializer(pConfig);
pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */
//pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS;
pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS;
pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry;
/*
* PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform.
* Always 0:0:0 on single NB platform.
*/
pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
/* Set HT path to NB by SbNode and SbLink */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
sbNode = (val >> 8) & 0x07;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
sbLink = (val >> 8) & 0x07; //assum ganged
pConfig->Northbridges[0].NbHtPath.NodeID = sbNode;
pConfig->Northbridges[0].NbHtPath.LinkID = sbLink;
//TODO: other NBs
#ifndef __PRE_RAM__
/* If temporrary MMIO enable set up CPU MMIO */
for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) {
UINT32 MmioBase;
UINT32 LinkId;
UINT32 SubLinkId;
MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress;
if (MmioBase != 0) {
LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf;
SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0;
/* Set Limit */
LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84),
AccessWidth32,
0x0,
((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6),
&(pConfig->Northbridges[i]));
/* Set Base */
LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80),
AccessWidth32,
0x0,
(MmioBase << 12) | 0x3,
&(pConfig->Northbridges[i]));
}
}
#endif
}

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src/mainboard/amd/dinar/rd890_cfg.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _RD890_CFG_H_
#define _RD890_CFG_H_
#include "NbPlatform.h"
#define RD890_IOAPIC_ADDR 0xC8000000
/* platform dependent configuration default value */
/**
* Path from CPU to NB
* [0..7] - Node (0..8)
* [8..11] - Link (0..3)
* [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
*/
#ifndef DEFAULT_HT_PATH
#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1
#define DEFAULT_HT_PATH {0x0, 0x3}
#endif
#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1
#define DEFAULT_HT_PATH {0x0, 0x1}
#endif
#endif
/**
* Bitmap of enabled ports on NB #0/1/2/3
* Bit[0] - Reserved
* Bit[1] - Reserved
* Bit[2] - Enable PCIe port 2
* Bit[3] - Enable PCIe port 3
* Bit[4] - Enable PCIe port 4
* Bit[5] - Enable PCIe port 5
* Bit[6] - Enable PCIe port 2
* Bit[7] - Enable PCIe port 7
* Bit[8] - Reserved
* Bit[9] - Enable PCIe port 9
* Bit[10]- Enable PCIe port 10
* Bit[11]- Enable PCIe port 11
* Bit[12]- Enable PCIe port 12
* Bit[13]- Enable PCIe port 13
* Example:
* port_enable = 0x14
* Port 2 and 4 enabled for training/initialization
*/
#ifndef DEFAULT_PORT_ENABLE_MAP
#define DEFAULT_PORT_ENABLE_MAP 0x0014
#endif
/**
* Bitmap of ports that have slot or onboard device connected.
* Example force PCIe Gen1 supporton port 2 and 4 (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4)
* #define DEFAULT_PORT_FORCE_GEN1 0x604
*/
#ifndef DEFAULT_PORT_FORCE_GEN1
#define DEFAULT_PORT_FORCE_GEN1 0x0
#endif
/**
* Bitmap of ports that have server hotplug support
*/
#ifndef DEFAULT_HOTPLUG_SUPPORT
#define DEFAULT_HOTPLUG_SUPPORT 0x0
#endif
#ifndef DEFAULT_HOTPLUG_DESCRIPTOR
#define DEFAULT_HOTPLUG_DESCRIPTOR {0, 0, 0, 0, 0, 0, 0, 0}
#endif
#ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS
#define DEFAULT_TEMPMMIO_BASE_ADDRESS 0xD0000000
#endif
/**
* Default GPP1 core configuraton on NB #0/1/2/3.
* 2 x8 slot, GFX_CONFIG_AABB
* 1 x16 slot, GFX_CONFIG_AAAA
*/
#ifndef DEFAULT_GPP1_CONFIG
#define DEFAULT_GPP1_CONFIG GFX_CONFIG_AABB
#endif
/**
* Default GPP2 core configuraton on NB #0/1/2/3.
* 2 x8 slot, GFX_CONFIG_AABB
* 1 x16 slot, GFX_CONFIG_AAAA
*/
#ifndef DEFAULT_GPP2_CONFIG
#define DEFAULT_GPP2_CONFIG GFX_CONFIG_AABB
#endif
/**
* Default GPP3a core configuraton on NB #0/1/2/3.
* 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1
* 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2
* 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3
* 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4
* 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5
* 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6
*/
#ifndef DEFAULT_GPP3A_CONFIG
#define DEFAULT_GPP3A_CONFIG GPP_CONFIG_GPP111111
#endif
/**
* Default HT Transmitter de-emphasis setting
*/
#ifndef DEFAULT_HT_DEEMPASIES
#define DEFAULT_HT_DEEMPASIES 0x3
#endif
/**
* Default APIC nterrupt base for IOAPIC
*/
#ifndef DEFAULT_APIC_INTERRUPT_BASE
#define DEFAULT_APIC_INTERRUPT_BASE 24
#endif
#define DEFAULT_PLATFORM_CONFIG(name) \
NB_PLATFORM_CONFIG name = { \
DEFAULT_PORT_ENABLE_MAP, \
DEFAULT_PORT_FORCE_GEN1, \
DEFAULT_HOTPLUG_SUPPORT, \
DEFAULT_HOTPLUG_DESCRIPTOR, \
DEFAULT_TEMPMMIO_BASE_ADDRESS, \
DEFAULT_GPP1_CONFIG, \
DEFAULT_GPP2_CONFIG, \
DEFAULT_GPP3A_CONFIG, \
DEFAULT_HT_DEEMPASIES, \
/*DEFAULT_HT_PATH,*/ \
DEFAULT_APIC_INTERRUPT_BASE, \
}
/**
* Platform configuration
*/
typedef struct {
UINT16 PortEnableMap; ///< Bitmap of enabled ports
UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2
UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug
UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors
UINT32 TemporaryMmio; ///< Temporary MMIO
UINT32 Gpp1Config; ///< Default PCIe GFX core configuration
UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration
UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration
UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level
// HT_PATH NbHtPath; ///< HT path to NB
UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC.
} NB_PLATFORM_CONFIG;
/**
* Bridge CIMx configuration
*/
void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig);
#endif //_RD890_CFG_H_

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <reset.h>
#include <arch/io.h> /*inb, outb*/
#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/
#define HT_INIT_CONTROL 0x6C
#define HTIC_BIOSR_Detect (1<<5)
#if CONFIG_MAX_PHYSICAL_CPUS > 32
#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
#else
#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
#endif
static inline void set_bios_reset(void)
{
u32 nodes;
u32 htic;
device_t dev;
int i;
nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
for(i = 0; i < nodes; i++) {
dev = NODE_PCI(i, 0);
htic = pci_read_config32(dev, HT_INIT_CONTROL);
htic &= ~HTIC_BIOSR_Detect;
pci_write_config32(dev, HT_INIT_CONTROL, htic);
}
}
void hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
}
//SbReset();
void soft_reset(void)
{
set_bios_reset();
/* link reset */
outb(0x06, 0x0cf9);
}

162
src/mainboard/amd/dinar/romstage.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
#include "superio/smsc/sch4037/sch4037_early_init.c"
#include "superio/smsc/sio1036/sio1036_early_init.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "pc80/i8254.c"
#include "pc80/i8259.c"
#include "nb_cimx.h"
#include "sb_cimx.h"
#include "Platform.h"
#include <arch/cpu.h>
#define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, SMSCSUPERIO_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
u32 agesawrapper_amdinitmmio (void);
u32 agesawrapper_amdinitreset (void);
u32 agesawrapper_amdinitearly (void);
u32 agesawrapper_amdinitenv (void);
u32 agesawrapper_amdinitlate (void);
u32 agesawrapper_amdinitpost (void);
u32 agesawrapper_amdinitmid (void);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sch4037_early_init (CONFIG_SIO_PORT);
/* Detect SMSC SIO1036 LPC Debug Card status */
if (detect_sio1036_chip(0x4E)) {
/* Found SMSC SIO1036 LPC Debug Card */
sio1036_early_init(0x4E);
}
post_code(0x31);
uart_init();
console_init();
/*
* SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
* Disable all Pcie Bridges to work around It.
*/
sr56x0_rd890_disable_pcie_bridge();
}
post_code(0x32);
val = agesawrapper_amdinitmmio();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n", val);
} else {
printk(BIOS_DEBUG, "agesawrapper_amdinitmmio passed\n");
}
/* Halt if there was a built in self test failure */
post_code(0x33);
report_bist_failure(bist);
// Load MPB
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
if(boot_cpu()) {
post_code(0x34);
sb_Poweron_Init();
}
post_code(0x35);
val = agesawrapper_amdinitreset();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
} else {
printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n");
}
post_code(0x36);
val = agesawrapper_amdinitearly ();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
} else {
printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n");
}
post_code(0x37);
nb_Poweron_Init();
post_code(0x38);
nb_Ht_Init();
post_code(0x39);
val = agesawrapper_amdinitpost ();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
} else {
printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n");
}
post_code(0x40);
val = agesawrapper_amdinitenv ();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
} else {
printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n");
}
/* Initialize i8259 pic */
post_code(0x41);
setup_i8259 ();
/* Initialize i8254 timers */
post_code(0x42);
setup_i8254 ();
post_code(0x43);
print_debug("Disabling cache as ram ");
disable_cache_as_ram();
print_debug("done\n");
post_code(0x44);
copy_and_run(0);
post_code(0x45); // Should never see this post code.
}

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src/mainboard/amd/dinar/sb700_cfg.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <string.h>
#include <console/console.h> /* printk */
#include "Platform.h"
#include "sb700_cfg.h"
/**
* @brief South Bridge CIMx configuration
*
* should be called before exeucte CIMx function.
* this function will be called in romstage and ramstage.
*/
void sb700_cimx_config(AMDSBCFG *sb_config)
{
if (!sb_config) {
printk(BIOS_DEBUG, "SB700 - Cfg.c - %s - No sb_config.\n", __func__);
return;
}
printk(BIOS_DEBUG, "SB700 - Cfg.c - %s - Start.\n", __func__);
memset(sb_config, 0, sizeof(AMDSBCFG));
/* SB_POWERON_INIT */
sb_config->StdHeader.Func = SB_POWERON_INIT;
/* header */
sb_config->StdHeader.pPcieBase = PCIEX_BASE_ADDRESS;
/* static Build Parameters */
sb_config->BuildParameters.BiosSize = BIOS_SIZE;
sb_config->BuildParameters.LegacyFree = LEGACY_FREE;
sb_config->BuildParameters.EcKbd = 0;
sb_config->BuildParameters.EcChannel0 = 0;
sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS;
sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS;
sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS;
sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS;
sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS;
sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS;
sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS;
sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS;
sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS;
sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS;
sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT;
sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS;
sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID;
sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID;
sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID;
sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID;
sb_config->BuildParameters.Ohci0Ssid = OHCI0_SSID;
sb_config->BuildParameters.Ohci1Ssid = OHCI1_SSID;
sb_config->BuildParameters.Ohci2Ssid = OHCI2_SSID;
sb_config->BuildParameters.Ohci3Ssid = OHCI3_SSID;
sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID;
sb_config->BuildParameters.Ehci0Ssid = EHCI0_SSID;
sb_config->BuildParameters.Ehci1Ssid = EHCI1_SSID;
sb_config->BuildParameters.SmbusSsid = SMBUS_SSID;
sb_config->BuildParameters.IdeSsid = IDE_SSID;
sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID;
sb_config->BuildParameters.LpcSsid = LPC_SSID;
sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS;
/* General */
sb_config->Spi33Mhz = 1;
sb_config->SpreadSpectrum = 0;
sb_config->PciClk5 = 0;
sb_config->PciClks = 0x1F;
sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood
sb_config->TimerClockSource = 2; // Auto
sb_config->S3Resume = 0;
sb_config->RebootRequired = 0;
/* HPET */
sb_config->HpetTimer = HPET_TIMER;
/* USB */
sb_config->UsbIntClock = 0; // Use external clock
sb_config->Usb1Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 18 Func0
sb_config->Usb1Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 18 Func1
sb_config->Usb1Ehci = 1; //0:disable 1:enable Bus 0 Dev 18 Func2
sb_config->Usb2Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 19 Func0
sb_config->Usb2Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 19 Func1
sb_config->Usb2Ehci = 1; //0:disable 1:enable Bus 0 Dev 19 Func2
sb_config->Usb3Ohci = 1; //0:disable 1:enable Bus 0 Dev 20 Func5
sb_config->UsbOhciLegacyEmulation = 1; //0:Enable 1:Disable
sb_config->AcpiS1Supported = 1;
/* SATA */
sb_config->SataController = 1;
sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci
sb_config->SataSmbus = 0;
sb_config->SataAggrLinkPmCap = 1;
sb_config->SataPortMultCap = 1;
sb_config->SataClkAutoOff = 1;
sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
//TODO: set to secondary not take effect.
sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled
sb_config->SataEspPort = 0;
sb_config->SataClkAutoOffAhciMode = 1;
sb_config->SataHpcpButNonESP = 0;
sb_config->SataHideUnusedPort = 0;
/* Azalia HDA */
sb_config->AzaliaController = AZALIA_CONTROLLER;
sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG;
sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN;
sb_config->pAzaliaOemCodecTablePtr = NULL;
#ifndef __PRE_RAM__
/* ramstage cimx config here */
if (!sb_config->StdHeader.pCallBack) {
sb_config->StdHeader.pCallBack = sb700_callout_entry;
}
//sb_config->
#endif //!__PRE_RAM__
printk(BIOS_DEBUG, "SB700 - Cfg.c - %s - End.\n", __func__);
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _SB700_CFG_H_
#define _SB700_CFG_H_
#include <stdint.h>
/**
* @def BIOS_SIZE_1M
* @def BIOS_SIZE_2M
* @def BIOS_SIZE_4M
* @def BIOS_SIZE_8M
*/
#define BIOS_SIZE_1M 0
#define BIOS_SIZE_2M 1
#define BIOS_SIZE_4M 3
#define BIOS_SIZE_8M 7
/* In SB700, default ROM size is 1M Bytes, if your platform ROM
* bigger than 1M you have to set the ROM size outside CIMx module and
* before AGESA module get call.
*/
#ifndef BIOS_SIZE
#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#define BIOS_SIZE BIOS_SIZE_2M
#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
#define BIOS_SIZE BIOS_SIZE_4M
#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
#define BIOS_SIZE BIOS_SIZE_8M
#endif
#endif
/**
* @def SPREAD_SPECTRUM
* @brief
* 0 - Disable Spread Spectrum function
* 1 - Enable Spread Spectrum function
*/
#define SPREAD_SPECTRUM 0
/**
* @def SB_HPET_TIMER
* @breif
* 0 - Disable hpet
* 1 - Enable hpet
*/
#define HPET_TIMER 1
/**
* @def USB_CONFIG
* @brief bit[0-6] used to control USB
* 0 - Disable
* 1 - Enable
* Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
* Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
* Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
* Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
* Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
* Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
* Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
*/
#define USB_CINFIG 0x7F
/**
* @def PCI_CLOCK_CTRL
* @breif bit[0-4] used for PCI Slots Clock Control,
* 0 - disable
* 1 - enable
* PCI SLOT 0 define at BIT0
* PCI SLOT 1 define at BIT1
* PCI SLOT 2 define at BIT2
* PCI SLOT 3 define at BIT3
* PCI SLOT 4 define at BIT4
*/
#define PCI_CLOCK_CTRL 0x1F
/**
* @def SATA_CONTROLLER
* @breif INCHIP Sata Controller
*/
#ifndef SATA_CONTROLLER
#define SATA_CONTROLLER 1
#endif
/**
* @def SATA_MODE
* @breif INCHIP Sata Controller Mode
* NOTE: DO NOT ALLOW SATA & IDE use same mode
*/
#ifndef SATA_MODE
#define SATA_MODE NATIVE_IDE_MODE
#endif
/**
* @breif INCHIP Sata IDE Controller Mode
*/
#define IDE_LEGACY_MODE 0
#define IDE_NATIVE_MODE 1
/**
* @def SATA_IDE_MODE
* @breif INCHIP Sata IDE Controller Mode
* NOTE: DO NOT ALLOW SATA & IDE use same mode
*/
#ifndef SATA_IDE_MODE
#define SATA_IDE_MODE IDE_LEGACY_MODE
#endif
/**
* @def EXTERNAL_CLOCK
* @brief 00/10: Reference clock from crystal oscillator via
* PAD_XTALI and PAD_XTALO
*
* @def INTERNAL_CLOCK
* @brief 01/11: Reference clock from internal clock through
* CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
*/
#define EXTERNAL_CLOCK 0x00
#define INTERNAL_CLOCK 0x01
#define SATA_CLOCK_SOURCE EXTERNAL_CLOCK
/**
* @def SATA_PORT_MULT_CAP_RESERVED
* @brief 1 ON, 0 0FF
*/
#define SATA_PORT_MULT_CAP_RESERVED 1
/**
* @def AZALIA_AUTO
* @brief Detect Azalia controller automatically.
*
* @def AZALIA_DISABLE
* @brief Disable Azalia controller.
* @def AZALIA_ENABLE
* @brief Enable Azalia controller.
*/
#define AZALIA_AUTO 0
#define AZALIA_DISABLE 1
#define AZALIA_ENABLE 2
/**
* @breif INCHIP HDA controller
*/
#ifndef AZALIA_CONTROLLER
#define AZALIA_CONTROLLER AZALIA_AUTO
#endif
/**
* @def AZALIA_PIN_CONFIG
* @brief
* 0 - disable
* 1 - enable
*/
#ifndef AZALIA_PIN_CONFIG
#define AZALIA_PIN_CONFIG 1
#endif
/**
* @def AZALIA_SDIN_PIN
* @brief
* SDIN0 is define at BIT0 & BIT1
* 00 - GPIO PIN
* 01 - Reserved
* 10 - As a Azalia SDIN pin
* SDIN1 is define at BIT2 & BIT3
* SDIN2 is define at BIT4 & BIT5
* SDIN3 is define at BIT6 & BIT7
*/
#ifndef AZALIA_SDIN_PIN
//#define AZALIA_SDIN_PIN 0xAA
#define AZALIA_SDIN_PIN 0x2A
#endif
/**
* @def GPP_CONTROLLER
*/
#ifndef GPP_CONTROLLER
#define GPP_CONTROLLER 1
#endif
/**
* @def GPP_CFGMODE
* @brief GPP Link Configuration
* four possible configuration:
* GPP_CFGMODE_X4000
* GPP_CFGMODE_X2200
* GPP_CFGMODE_X2110
* GPP_CFGMODE_X1111
*/
#ifndef GPP_CFGMODE
#define GPP_CFGMODE GPP_CFGMODE_X1111
#endif
/**
* @brief South Bridge CIMx configuration
*
*/
void sb700_cimx_config(AMDSBCFG *sb_cfg);
/**
* @brief Entry point of Southbridge CIMx callout
*
* prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
*
* @param[in] func Southbridge CIMx Function ID.
* @param[in] data Southbridge Input Data.
* @param[in] sb_cfg Southbridge configuration structure pointer.
*
*/
u32 sb700_callout_entry(u32 func, u32 data, void* sb_cfg);
#endif //_SB700_CFG_H_